With the rumors about UFS going mainstream with first introduction in Samsung Galaxy S6 phone expected next year (2015), I wanted to raise what I see as a repeat concern when discussing adoption of new standard (such as UFS). A key challenge in today’s mobile IC and electronics design is the ability to meet time to market window, get your system up and running with new standards and interoperate with other devices. This is particularly true for JEDEC UFS v2.0 which is fairly new standard that the indusrty is gearing up to mass production of the first UFS devices and Application Processors targeted to be available in the hands of customers in 2015.
MIPI Alliance’s M-PHY specification v3.0 provides a solid specification targeted to a variety of applications in the mobile electronics space. I hear some concerns about that this technology is new and engineers prefer to wait for the adoption to pick up before they use it.
MIPI M-PHY is a promising technology, intended to be used across multiple applications and utilized by standard organizations such as JEDEC for UFS, USB for SSIC, and PCI-SIG for Mobile PCIe. We have been working in the past several months to develop and prove M-PHY in HS-Gear3 operation as the specification evolves in the MIPI PHY Work group. Our deep involvement in the group allowed us to develop the M-PHY which is fully compliant to the latest M-PHY v3.0 specification. In March 2013 during the MIPI Face-to-face meeting we demonstrated M-PHY operation in HS-Gear3 and showed it to everyone on the floor. I received a lot of requests to share the video of this demo and now it is ready.
Discussing and sharing opinions is what drives our industry forward; however sharing ideas becomes more challenging in our time where competition is intense. This is true for any industry but even more relevant to the high-pace mobile market where wrong move can cost you a fortune. It is that important then to stay connected and aligned with market trends so you’re not caught off guard and mitigate design and market risks while enabling to take a leadership position.
The MIPI alliance announced the release of M-PHY v3.0 in Barcelona which solidifies the Gear3 and other specs enhancements. From the press release I can quote this:M-PHY® v3.0 delivers a low-power, scalable physical layer with a data rate range nearing 6Gbps. CSI-3 has been adopted and is available for MIPI Alliance members. LLI v2.0 and M-PHY® v3.0 are scheduled for adoption by the end of April 2013.
I spent last week at Mobile World Congress 2013 in Barcelona, where Synopsys also demonstrated our D-PHY, CSI-2 and DSI protocols running in hardware and connecting to Agilent test equipment and UNH conformance test suite.
Toshiba’s launch of the Industry’s First Embedded NAND Flash memory module compliant with JEDEC UFS v1.1 marks an impressive milestone for the mobile storage market space.
I want to share a video showing the work we are doing at Synopsys to help semiconductor vendors adopt the JEDEC UFS v1.1 standard needed for high performance storage applications. The video shows the Synopsys UFS Host solution connecting with the Toshiba UFS Device prototyping platform and operating a sequence of read and write commands. These commands are sent from the host to the device to store and fetch the data from on-board NVM using the UFS link. As you can expect we have done more comprehensive interoperability tests beyond that.
Mobile devices that use baseband processors and RFIC’s require a lot of effort to integrate these componenets together in a very challenging environment: small and slim board, tight casing, lots of RF components that may cause noise. Adding to that integrating new interface between the baseband processor and RFIC makes this integration work even more difficult. Synopsys can assist and reduce the integration risk and interface adoption easy for those who selects to integrate this kind of interface, namely the DigRFv4. Here’s a short video that demonstrates our integration effort with hardware prototyping system that emulates the baseband processor DigRFv4 interface and connects to Fujitsu RFIC hardware system.