Many customers approached us in the last year inquiring about I3C, its benefits and market adoption. The I3C benefits compared to other Sensor interfaces used today, such as I2C and SPI are clear. There are many sensor interfaces which cause unnecessary fragmentation, and are not optimized for system power efficiently for communication with sensors. These drawbacks limit applications and scalability for usage of sensors in mobile, IoT, embedded, automotive environments.
Microsoft shared some interesting details about their 28nm SoC design targeting augmented reality headset. Well, that is not just a processor, it’s custom vision processor which Microsoft calls HoloLens Processing Unit (HPU) as it is specifically targeting the augmented (possibly also virtual) reality needs. It is very interesting to see the computing power that was implemented on the chip to accommodate the imaging algorithms that used. The interfaces used on this chip are referenced as PCIe, DDR and MIPI. As the HPU uses several camera interfaces, depth and motion sensor for image identification and processing, recognizing gestures it’s clear that MIPI Camera and Display interfaces are probably used extensively. As per the die plot provided, the MIPI interfaces take a very small area of the processor compared to the computing blocks that are dominant utilizing 24 cores.
As electronics become smarter, require less human intervention, the machines around us are capable of doing more, making decisions based on environment and conditions. To facilitate that more sensors are used in electronics devices, it is common to see >12 sensors in latest smartphones used in the market, but this smarter device trend goes beyond mobile to markets such as consumer, industrial and automotive.
I just came back from the MIPI alliance face-to-face meeting last week that was engaging and interesting.
In the last post I asked what is MIPI Alliance’s most popular specification in terms of adoption as of today.
Posted in Application processor, Baseband processor, Camera, CSI, D-PHY, DigRF, Display, DSI, Image signal processor, LLI, M-PHY, MIPI alliance, Mobile PCIe, RFFE, RFIC, SLIMbus, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro |
In my last post I was discussing how to reduce display data transmission using Display Compression technology. Reducing transmitted traffic while supporting a higher link rate allows to reduce pin count, power consumption and area (cost) of implementation. In the Oct’15 MIPI Face-to-face meeting we (Synopsys) showed the Industry’s first DPHY v1.2 operating at 2.5Gbps/lane with 16nm silicon running at 2.5Gbps. We used a setup that had two D-PHY testchip boards, one D-PHY acting as Rx and another D-PHY acting as Tx connecting to test equipment to provide stimulus and capture the results.
We live in a challenging era where a lot of information is presented to us and it is hard distill what’s important and where to invest our time.
With the rumors about UFS going mainstream with first introduction in Samsung Galaxy S6 phone expected next year (2015), I wanted to raise what I see as a repeat concern when discussing adoption of new standard (such as UFS). A key challenge in today’s mobile IC and electronics design is the ability to meet time to market window, get your system up and running with new standards and interoperate with other devices. This is particularly true for JEDEC UFS v2.0 which is fairly new standard that the indusrty is gearing up to mass production of the first UFS devices and Application Processors targeted to be available in the hands of customers in 2015.
I spent last week at Mobile World Congress 2013 in Barcelona, where Synopsys also demonstrated our D-PHY, CSI-2 and DSI protocols running in hardware and connecting to Agilent test equipment and UNH conformance test suite.
I want to share a video showing the work we are doing at Synopsys to help semiconductor vendors adopt the JEDEC UFS v1.1 standard needed for high performance storage applications. The video shows the Synopsys UFS Host solution connecting with the Toshiba UFS Device prototyping platform and operating a sequence of read and write commands. These commands are sent from the host to the device to store and fetch the data from on-board NVM using the UFS link. As you can expect we have done more comprehensive interoperability tests beyond that.