Microsoft shared some interesting details about their 28nm SoC design targeting augmented reality headset. Well, that is not just a processor, it’s custom vision processor which Microsoft calls HoloLens Processing Unit (HPU) as it is specifically targeting the augmented (possibly also virtual) reality needs. It is very interesting to see the computing power that was implemented on the chip to accommodate the imaging algorithms that used. The interfaces used on this chip are referenced as PCIe, DDR and MIPI. As the HPU uses several camera interfaces, depth and motion sensor for image identification and processing, recognizing gestures it’s clear that MIPI Camera and Display interfaces are probably used extensively. As per the die plot provided, the MIPI interfaces take a very small area of the processor compared to the computing blocks that are dominant utilizing 24 cores.
I just came back from the MIPI alliance face-to-face meeting last week that was engaging and interesting.
In the last post I asked what is MIPI Alliance’s most popular specification in terms of adoption as of today.
Posted in Application processor, Baseband processor, Camera, CSI, D-PHY, DigRF, Display, DSI, Image signal processor, LLI, M-PHY, MIPI alliance, Mobile PCIe, RFFE, RFIC, SLIMbus, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro
I got several inquiries about adoption rate of physical layers across the mobile and adjacent industries after posting the video showing D-PHY v1.2 silicon on 16nm I realize that it’s debatable if it’s fair to compare one spec vs the other. However, I would like to note that de-facto standard has a lot of weight and it is what sets it apart compared to other potential specifications which only a few vendors select. Once a certain standard is well adopted across the industry, it establishes an entrenched position and cannot be replaced instantly. Any potential replacement standard need to take into consideration backwards compatibility to ensure vendor’s investment in the de-facto standard continues to bear fruits. It requires a phased approach towards replacing a successful standard and it’ll only be possible if the replacement standard has proven benefits compared to the de-facto standard and that the transition period is not long and not painful.
In my last post I was discussing how to reduce display data transmission using Display Compression technology. Reducing transmitted traffic while supporting a higher link rate allows to reduce pin count, power consumption and area (cost) of implementation. In the Oct’15 MIPI Face-to-face meeting we (Synopsys) showed the Industry’s first DPHY v1.2 operating at 2.5Gbps/lane with 16nm silicon running at 2.5Gbps. We used a setup that had two D-PHY testchip boards, one D-PHY acting as Rx and another D-PHY acting as Tx connecting to test equipment to provide stimulus and capture the results.
Does your SoC Display interface implementation looks like this?
We live in a challenging era where a lot of information is presented to us and it is hard distill what’s important and where to invest our time.
I am often asked when meeting with customers about latest trends and what would be the right interface for the customer next design. The answer of course depends on which market you go after, your cost targets and more, however being aware of the latest trends help in the decision.
With the rumors about UFS going mainstream with first introduction in Samsung Galaxy S6 phone expected next year (2015), I wanted to raise what I see as a repeat concern when discussing adoption of new standard (such as UFS). A key challenge in today’s mobile IC and electronics design is the ability to meet time to market window, get your system up and running with new standards and interoperate with other devices. This is particularly true for JEDEC UFS v2.0 which is fairly new standard that the indusrty is gearing up to mass production of the first UFS devices and Application Processors targeted to be available in the hands of customers in 2015.
MIPI Alliance’s M-PHY specification v3.0 provides a solid specification targeted to a variety of applications in the mobile electronics space. I hear some concerns about that this technology is new and engineers prefer to wait for the adoption to pick up before they use it.