In my last post I was discussing how to reduce display data transmission using Display Compression technology.
Reducing transmitted traffic while supporting a higher link rate allows to reduce pin count, power consumption and area (cost) of implementation.
In the Oct’15 MIPI Face-to-face meeting we (Synopsys) showed the Industry’s first DPHY v1.2 operating at 2.5Gbps/lane with 16nm silicon running at 2.5Gbps. We used a setup that had two D-PHY testchip boards, one D-PHY acting as Rx and another D-PHY acting as Tx connecting to test equipment to provide stimulus and capture the results.
The diagram below shows how D-PHY v1.2 speeds of 2.5G can be utilized to send all transmitted information over a single data lane, with DSC compression:
The combination of compression and high bandwidth for displays, higher pixel rate for image sensors is driving the wide adoption of D-PHY v1.2 across the industry, improving system flexibility and deploying cost effective implementations. The MIPI D-PHY continuous to be the physical interface of choice for camera and display interfaces in mobile and beyond-mobile applications and its progression towards faster speeds, longer channel lengths strengthens the eco-system and its dominant market position.
In case you missed the MIPI event in Oct, here’s a quick video we took showing the setup:
Yes, Synopsys is first to market with a proven D-PHY v1.2 solution and competitors will follow which will strengthen the eco-system and allow more options. Being first doesn’t only mean that we can service the first adopters which is obviously true. It also means the ability to service (and most likely having) more customers, more maturity in design and in production. At the end of the day, IP vendors service the eco-system in enabling customers adopt a technology, making it a lower risk investment and helping customers get to market faster.
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