Microsoft shared some interesting details about their 28nm SoC design targeting augmented reality headset. Well, that is not just a processor, it’s custom vision processor which Microsoft calls HoloLens Processing Unit (HPU) as it is specifically targeting the augmented (possibly also virtual) reality needs. It is very interesting to see the computing power that was implemented on the chip to accommodate the imaging algorithms that used. The interfaces used on this chip are referenced as PCIe, DDR and MIPI. As the HPU uses several camera interfaces, depth and motion sensor for image identification and processing, recognizing gestures it’s clear that MIPI Camera and Display interfaces are probably used extensively. As per the die plot provided, the MIPI interfaces take a very small area of the processor compared to the computing blocks that are dominant utilizing 24 cores.
As electronics become smarter, require less human intervention, the machines around us are capable of doing more, making decisions based on environment and conditions. To facilitate that more sensors are used in electronics devices, it is common to see >12 sensors in latest smartphones used in the market, but this smarter device trend goes beyond mobile to markets such as consumer, industrial and automotive.
I got several inquiries about adoption rate of physical layers across the mobile and adjacent industries after posting the video showing D-PHY v1.2 silicon on 16nm I realize that it’s debatable if it’s fair to compare one spec vs the other. However, I would like to note that de-facto standard has a lot of weight and it is what sets it apart compared to other potential specifications which only a few vendors select. Once a certain standard is well adopted across the industry, it establishes an entrenched position and cannot be replaced instantly. Any potential replacement standard need to take into consideration backwards compatibility to ensure vendor’s investment in the de-facto standard continues to bear fruits. It requires a phased approach towards replacing a successful standard and it’ll only be possible if the replacement standard has proven benefits compared to the de-facto standard and that the transition period is not long and not painful.
In my last post I was discussing how to reduce display data transmission using Display Compression technology. Reducing transmitted traffic while supporting a higher link rate allows to reduce pin count, power consumption and area (cost) of implementation. In the Oct’15 MIPI Face-to-face meeting we (Synopsys) showed the Industry’s first DPHY v1.2 operating at 2.5Gbps/lane with 16nm silicon running at 2.5Gbps. We used a setup that had two D-PHY testchip boards, one D-PHY acting as Rx and another D-PHY acting as Tx connecting to test equipment to provide stimulus and capture the results.