Posted by Hezi Saar on June 8, 2011
We are back with the continued interview with Eric Esteve of IP Nest. Check previous posts for Q&A we covered earlier.
Q: You are projecting a very strong growth for these interfaces, almost 100% from 2010 to 2015. How do you explain this growth with your prediction you made about lower number of design starts going forward?
A: First, I should precise that different predictions, from different analyst, like Gartner has proposed during IP-SoC in December 2010, show a lower growth. Gartner’s prediction made at IP-SoC was a 4 to 5% CAGR for the overall IP market. The above prediction is for the Interface IP market only, and shows a 14% CAGR for 2010-2015.
Q: That’s interesting distinction between Gartner’s growth numbers and yours, what are the reasons for doubling the interface IP market while design starts decline?
A: The first reason is structural: yes the number of design starts per year declines at a 2 to 4% yearly rate, but the nature of the ASIC or ASSP SoC designs strongly change. The SoC for Wireless (Application Processor) or Multimedia for example can easily integrate several dozens (maybe up to 100?) IP functions (externally or internally sourced). Less design starts, but a growing number of IP per design. This being true for SoC and also for mixed signal ASSP, even if the nature of the IP used here is different. What is important is that IP usage has become an essential part of the design methodology, and this is a long term trend as this is a part of the answer to the “design rupture”: with a gate count per square mm in the 300 to 500 K gates, and when you know that the sweet spot is a die size of 40 sq mm (for many reasons linked with wafer size, yield, packaging and so on), you can only “fill” this die (equivalent to 10 to 15 Million gates) with pre designed function.
We know that many designs which were ASIC in 1995 or 2000 are using FPGA technology in 2011, this is one important reason why the number of ASIC/ASSP design starts is declining. But this is good for the IP business too! Even if the price for an FPGA license for a certain function is much smaller than for an ASIC license, and if the large FPGA vendors tend to propose their own IP for strategic reasons, “somebody” has to design the function, validate it and package it to create an IP. Who could do it better than an IP vendor? So, the FPGA market is generating a decent revenue flow, even if the end user will not necessarily deal directly with the IP vendor. Just think about Altera sourcing the PCI Express Gen-2 “Hard IP” to IP vendor, a multi-million dollar deal! Or Xilinx sourcing their multi standard SerDes to another IP vendor… Even if the strong growth of the FPGA market is obviously bad for ASIC vendor, it is still good for the IP vendors.
Finally, last but not least, the reason why the Interface IP segment will see a strong growth is due to the fact that the old, parallel type, interface technology is vanishing to the benefit of the High Speed serial type. Which was a “no cost” I/O becomes a 5 GHz SerDes, much too complex to design for most of design teams, and a new function has appeared: the Controller. Even if most of the designers could spend the time necessary to build the ad-hoc Controller for a certain protocol (USB, PCIe, SATA…), it would bring no differentiation, use resources, so the most reasonable choice is to source it as an IP. Since I am in the Interface IP business (2005) I have seen the emergence of: PCI Express Gen-2, SATA 3, HDMI 1.3, DDR3 and the move to DDR hard PHY instead of soft PHY, PCI Express Gen-3, SATA 6, USB 3.0, the different MIPI specifications (more than 8 different) and associated PHY, DDR4… and I forget to mention DisplayPort, SerialRapidIO, Infiniband, Hyper Transport and more! All of these did not exist before and are displacing the previously used interface technologies, parallel based. They are not trivial to design, but bring no differentiation, so this is a new market, which did not exist before. Because the end user, the person who buys the final product, has become familiar with these high speed serial protocols, the OEM tend to integrate more and more of these. Just think about a Set-Top-Box supporting now HDMI, SATA and USB 3.0. To summarize, yes, I expect the interface IP market to double from 2010 and reach $500M in 2015, thanks to the move from parallel to serial, because buying makes more sense than making, because the constantly growing SerDes speed allows escaping the commoditization and price decline and the use of high speed interface, previously reserved to happy few using fire-wire with Apple computer, has democratized and my 70 years old mother uses probably five to ten products integrating one of these interfaces!
Q: What are the challenges for the MIPI alliance as you see it?
A: The first challenge was to issue the set of specifications and to have all the members (contributors) agreeing on these. This very important step is now completed. Last year (2010) has been the start of a marketing campaign, which is still ongoing. The goal is to popularize MIPI among the electronic industry, starting with the companies working in the wireless handset, and more specifically in the smartphone applications, and try to promote MIPI usage among the companies involved in the overall wireless handset –features phones and even low cost phone. Then, the next step will be to promote MIPI usage in the mobile industry in general. When, and if, MIPI will be used in Media Tablet or Netbooks, or in the gaming industry, we could say that the MIPI Alliance has done the job, and even more than was initially forecasted!
Q: What are the popular MIPI specifications you believe are hot and why?
A: As you know, MIPI specifications define a PHY and a Controller, the second being specifically adapted to a certain type of IC to interface with, like Camera Controller, Display and so on.
If we start with the PHY, which is by nature a mixed signal function, I think the M-PHY is a very hot product. Why? If I had to jump start and use MIPI for CSI, DSI, LLI or DigRF, and even if I could use the D-PHY (the first version of the MIPI PHY) I would directly use the M-PHY. Because it could be used across several generation of IC, and as the M-PHY will progressively replace the D-PHY for every specification.
If we look now at the functional specifications for the different controllers, the adoption for CSI, DSI and DigRF depends on the decision taken by the different chip makers (Camera Controller, Display Controller and Modem), I would expect them to massively move to MIPI – if it is not already done- because of the real advantages of using a common specification, especially if the OEMs are pushing!
It will be interesting to see how quickly LLI specification, just released at the end of 2010, will be adopted. Here we are not only talking about a more rational approach, but the implementation of LLI in a system (a handset or a Media Tablet) can help to save DRAM device, we commonly hear about a $2 saving on DRAM chip. This is huge when you manufacture system by dozen of million!
Also, I will carefully monitor the adoption rate for UniPro and UFS, for which the versions 1.4 and 1.0 respectively have been very recently finalized. As for the first, it brings networking capabilities to enable sharing of resources in a multi master environment, as such we can expect the system architects to be creative and imagine smart usage of UniPro, and for UFS an interface specification which has been adopted by JEDEC, according with the MOU signed with the MIPI Alliance.
Q: What are your thoughts about the standards (or lack of) that MIPI specifications are competing against in display, camera, interconnect, RF applications?
A: If we take the display application as an example, we can say that everybody agrees about the fact the old, LVDS based, interconnect technique should be replaced. The DisplayPort specification has been issued back in 2006, and it took quite a long time before it started to be adopted. When you think about it, you realize that the power consumption associated with DisplayPort is not well suited with the Mobile Handset. If you only need to support a medium bandwidth, you will use a DSI-1 interface (and the D-PHY) rather than DisplayPort. It is only when you need for a higher bandwidth that DisplayPort could be in competition with DSI-2 (and the M-PHY), as it appears to be the case with the Media Tablet from a well known, successful OEM.
Interconnect: the pervasion of PCIe and USB in almost every market segment could be seen as a competitor for some of the MIPI interconnect, but the power consumption is a key factor for the mobile industry. In fact, we are seeing the MIPI pervasion in the other segments, as a MOU has just been signed between the MIPI Alliance and USB-IF, allowing to use MIPI M-PHY instead of the classical USB 3.0 PHY, to support SuperSpeed USB interconnect (still using the USB 3.0 Controller)!
Camera and RF applications: we don’t really know which competing standard or specification could be used, even if we are aware of the use of USB HSIC in some application processor to interface with the modem.
If you want to purchase one of Eric’s reports, go here (http://www.ip-nest.com/index.php?page=wired) or email here (firstname.lastname@example.org).
Check this blog soon for our next Q&A with Eric including forecast and views about the mobile industry.
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Views and Trends in mobile electronics connectivity related to MIPI IP
I started my career as an R&D engineer for embedded systems, then transitioned into applications engineering and product marketing roles in the semiconductor industry. With my systems knowledge, I have led many IC design wins that have enabled portable applications such as cellular phones, digital cameras and eBooks.
What intrigues me about the mobile electronics market is how rapid technological innovations, economic forces and changing consumer preferences drive market direction. Let’s explore these developments together.
– Hezi Saar