Magic Blue Smoke

Isolation cells are used in almost all power gated designs.  Given below are some tips about these cells, this information is based on my experience working with various designers.  (1) Output signal isolation is usually a better choice than the input isolation . (2) Input isolation is reasonable on designs that have controllable independent power […]

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  My apologies for changing the title of my previous post. I realized that most of the optimization challenges are primarily due to the design requirements not UPF requirements. UPF is just a medium to define power intent, similar to verilog defining the logic intent of the design. continuing on the same topic, few more […]

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  I quite often get this question, my design used to work fine , P&R tools did not have any issues and was routed clean and so was LVS . But the same design, targeted towards reducing power leads to undesirable results and not at all clean? Now lets look at some of the challenges […]

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  Continuing on the same topic, here are are some thoughts on the insertion criteria   if planning for decoupling cap in the power planning stage, a good strategy would be, to add as many decoupling cap as possible in the permanent power network at the positions close to the switch cells for maximum effectiveness […]

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Hearing many concerns on topics related to power gated design and its relation to decoupling capacitor to reduce IR-Drop issues. Thought of writing a paragraph on this topic. Power gated designs requires addition of decoupling capacitor  to power network to resolve dynamic IR-drop issues.  Decoupling cap insertion becomes more challenging in the power-gated designs compared […]

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  This year at DAC its once again “Low Power is one of the biggest challenges ”   Here is a link explaining a bit on Low Power at DAC “Low Power and DAC”

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Recently found some interesting information on how to write proper level shifter rule, when designer does not want to insert LS in one particular direction. For example say, we don’t want tools to insert High to Low LS. If we go by traditional approach as given below set_level_shifter -domain LOW -applies_to outputs -rule low_to_high -location […]

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Quite often I am seeing, different switch cells are used in parallel(controlled turn-on) to shut-down power to a block. If someone need to write an UPF, it would  look something like this   create_power_switch gprs_sw_0   -domain GPRs/GPRS   -input_supply_port {in GPRs/VDDG}   -output_supply_port {out GPRs/VDDGS}   -control_port {gprs_sd PwrCtrl/gprs_sd}   -on_state {sw_0_on_state in {!gprs_sd}} […]

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Working on hierarchical UPF flows these days, its quite interesting to observe how tools optimize PST hierarchically and also on how to constrain/write UPF for lower level blocks.     There are quite a few challenges in terms of UPF with respect to   (a) Location of special cells such as LS/ISO/ELS…etc (b) Depending on […]

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Wow again it was a long break from blogging, was very very busy. During this time I happened to come across simulating a gate level design with power and ground. Simulation ran ok and there was no issue detected, but when a static rule checking was run, static checks using MVRC detected that PG connection […]

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