Isolation cells are used in almost all power gated designs. Given below are some tips about these cells, this information is based on my experience working with various designers.
Hearing many concerns on topics related to power gated design and its relation to decoupling capacitor to reduce IR-Drop issues. Thought of writing a paragraph on this topic.
Recently found some interesting information on how to write proper level shifter rule, when designer does not want to insert LS in one particular direction.
Quite often I am seeing, different switch cells are used in parallel(controlled turn-on) to shut-down
Working on hierarchical UPF flows these days, its quite interesting to observe how tools optimize PST hierarchically and also on how to constrain/write UPF for lower level blocks.
Wow again it was a long break from blogging, was very very busy. During this time I happened to come across simulating a gate level design with power and ground. Simulation ran ok and there was no issue detected, but when a static rule checking was run, static checks using MVRC detected that PG connection were broken!. I thought gate level simulation should have caught it because we had verilog simulation models with PG as shown below
- Godwin Maben