Magic Blue Smoke

Archive for the 'Architecture' Category

 

Physical Structure of Special Cells (Cont’d)

last week we saw physical structure of LS/ISO cells. Today lets look at

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Posted in Architecture, low power general |

 

UPF Overview Part II

Wish you all a very Happy and Prosperous New Year. Hope you all had a good holiday season.

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Posted in Architecture |

 

UPF Overview Part I

UPF is a way to represent the Power Intent of a design. It directs all the tools in the flow to interpret the Power Intent in the same way. Before we jump into the details of UPF, let’s try to understand what we mean by Power Intent.

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Posted in Architecture |

 

Managing IR Drop Issues in General

Most common issue faced in any Low Power Design is how can we minimize noise coupling between different rails and between cells in the same power domain. I am planning on discussing these in my next 2 posts.

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Posted in Architecture |

 

DVFS Impacts Timing Closure

I was in discussion with a designer other day on “Impact on performance of the design if the voltage range is not choosen correctly”, today I am going elaborate a bit on this topic.

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Posted in Architecture |

 

Voltage/Frequency Scaling Mechanisms

I was in Boston last week attending SNUG and got a chance to interact with many designers and one of the key concerns raised were in understanding the Voltage scaling approach . Planning to take a quick tour on this topic in my next few posts

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Posted in Architecture |

 

Simulating Retention behaviour using UPF

Last week, we saw on how to simulate retention flops using $functions as well as using adhoc methods to simulate similar behaviour. We have been hearing a lot about power standards helping us in solving this problem. Here is how UPF can help us in simulating this behaviour

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Posted in Architecture |

 

Simulating Retention Behaviour

In my earlier posts we discussed retention mechanisms. Today lets look at how to simulate this at RTL Level.

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Posted in Architecture |

 

Retention Mechanisms used in a Power Gated Design (Cont’d)

In the last 2 posts, we discussed how retentions cells look like and what are the advantages/disadvantages. Since most of the designs do have memories and they tend to be shut-down, how is the state of memory retained ? We cannot reload the data from external memory into the local memory. Today let’s see how this is accomplished.

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Posted in Architecture |

 

Retention Mechanisms used in a Power Gated Design (Cont’d)

Last week, we discussed about the type of retention registers available. In this post let me highlight few more points

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Posted in Architecture |