Magic Blue Smoke

Archive for the 'Architecture' Category

 

Physical Structure of Special Cells (Cont’d)

last week we saw physical structure of LS/ISO cells. Today lets look at (a) Retention Registers: These are typically either dual height cells or single height wide cells. They have Primary Rail and Secondary Rail. Primary Rail is switchable and Secondary Rail supplies power, when Primary Rail is off. They are typically placed in a […]

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Posted in Architecture, low power general | 11 Comments »

 

UPF Overview Part II

Wish you all a very Happy and Prosperous New Year. Hope you all had a good holiday season. In the last post we saw how UPF answers our questions with respect to the power behaviour of a design. Today lets look at how the various commands in UPF are catergorised. (1) Power Domain Related create_power_domain […]

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UPF Overview Part I

UPF is a way to represent the Power Intent of a design. It directs all the tools in the flow to interpret the Power Intent in the same way. Before we jump into the details of UPF, let’s try to understand what we mean by Power Intent. Typically for any design implementing any of the […]

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Managing IR Drop Issues in General

Most common issue faced in any Low Power Design is how can we minimize noise coupling between different rails and between cells in the same power domain. I am planning on discussing these in my next 2 posts. Power and Ground Noise can degrade timing and can lead to functional failures. Most commonly used method […]

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DVFS Impacts Timing Closure

I was in discussion with a designer other day on “Impact on performance of the design if the voltage range is not choosen correctly”, today I am going elaborate a bit on this topic. While designing the system with DVFS techniques, we need to look at the impact of temperature inversion on the performance of […]

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Voltage/Frequency Scaling Mechanisms

I was in Boston last week attending SNUG and got a chance to interact with many designers and one of the key concerns raised were in understanding the Voltage scaling approach . Planning to take a quick tour on this topic in my next few posts There are various voltage scaling approaches that are in use today […]

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Posted in Architecture | 8 Comments »

 

Simulating Retention behaviour using UPF

Last week, we saw on how to simulate retention flops using $functions as well as using adhoc methods to simulate similar behaviour. We have been hearing a lot about power standards helping us in solving this problem. Here is how UPF can help us in simulating this behaviour set_retention gated_retention -domain IGATED_DOMAIN -retention_power_net VDD -retention_ground_net […]

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Simulating Retention Behaviour

In my earlier posts we discussed retention mechanisms. Today lets look at how to simulate this at RTL Level. As we all know, today MV Simulation can be accomplished using some standard power formats such as UPF/CPF. Since some of these are not in full production, I quite often get this question : “How do […]

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Retention Mechanisms used in a Power Gated Design (Cont’d)

In the last 2 posts, we discussed how retentions cells look like and what are the advantages/disadvantages. Since most of the designs do have memories and they tend to be shut-down, how is the state of memory retained ? We cannot reload the data from external memory into the local memory. Today let’s see how […]

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Posted in Architecture | 3 Comments »

 

Retention Mechanisms used in a Power Gated Design (Cont’d)

Last week, we discussed about the type of retention registers available. In this post let me highlight few more points Pro’s and Con’s of Single Pin Vs Dual Pin retention flops: Advantages of Single Pin: Minimal area impact Single signal controls retention Disadvantages of Single Pin: Performance Impact on the register Hold Time requirements for […]

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