Magic Blue Smoke


Multi-Voltage/Power Gated design and LVS


Some interesting observation while running LVS on a power gated or a MV design. Here is quick preview on the problem description



As shown in the picture above if LVS is run on a Verilog netlist generated without bulk pin connections, bulk connections may not be correct from electrical perspective.

More on how typically designers handle this in my next post.


One response to “Multi-Voltage/Power Gated design and LVS”