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Clock Gating State Retention

Recently came across this request for clock gating retention latch. Here are some details on why these are required and what it means to the design.

Clock gating is the most common low power saving technique in use for a long time.  Latch based clock gating logic is typically used to avoid any glitches even during entry and exit from/to sleep mode.  In a power gated design , usually we stop the clock at in-active phase before retaining states and entering sleep mode and same for wake up mode.  Here one of the main challenge is the validity of the enable signal at wakeup, which is typically provided by the restored states in the registers propagating through cloud of logic to the clock gating latches, which stay open during in-active phase.

In a power gated design, where retention registers are not used, this propagation mechanism may not work and we might have to use some kind of state retention for the clock gating latches, which retains the clock gating state when powered down. In one of the design, this is incorporated using retention latch(similar to retention flop) inside the latch based clock gating cell.

It may not be required to use these special cells if retention registers happen to exist in the design, which controls the clock enable signal state. Its also not required if some logic is built in to ensure controllability of the clock during inactive phase while entering and exiting the hibernation mode.