Posted by Godwin Maben on October 29, 2009
Isolation cells are used in almost all power gated designs. Given below are some tips about these cells, this information is based on my experience working with various designers.
(1) Output signal isolation is usually a better choice than the input isolation .
(2) Input isolation is reasonable on designs that have controllable independent power domains
(3) If custom isolation cells are not available, regular cells such as (AND/NOR) can be used, but we need to make sure that these cells are kept alive all the time.
(4) Isolation cells impacts timing and area and hence should be used and analyzed properly. It should be inserted as early as possible in the design cycle to account for area/timing penalty.
(5) If feed through paths exist in the power down domain, its not necessary to isolate these nets , but need to be kept alive
(6) Isolation cells should be placed close to boundary and interface nets should be protected all the time and should not be buffered if its residing in a domain, whose power characteristics is different from source/sink domain
(7) Some logic cells such as XOR gates, should be avoided at the interface logic so as to prevent any accidental sneak paths
(8) Check the isolation states to make sure, parking at one value “1” or “0” does not lead to any sneaky paths
(9) Its preferable to use enable level shifter instead of LS+ISO cells .
(10) Last but not the least, make sure to write the isolation policy in UPF at the right interface. Its not practical and reasonable to write isolation policy both at the sink/source simultaneously.
Lets discuss about the placement of these cells and AON’ness of these cells in the next post.
- Godwin Maben