Posted by Godwin Maben on May 11, 2009
Wow again it was a long break from blogging, was very very busy. During this time I happened to come across simulating a gate level design with power and ground. Simulation ran ok and there was no issue detected, but when a static rule checking was run, static checks using MVRC detected that PG connection were broken!. I thought gate level simulation should have caught it because we had verilog simulation models with PG as shown below
input A, B, VDD, VSS;
wire A, B, Y;
assign Y = ((VDD===1’b1) & (VSS === 1’b0))?(A&B):1’bx;
Now in the verilog gate level netlist, all the power/ground ports/pins are declared as “supply” data type. Now as per the verilog LRM, supply1/supply0 has the strongest strength and hence even if the input to this module is unconnected(typically “Z” in simulation), this gets overridden by supply statements and hence VDD/VSS is seen as “1” and “0”. Because of this behavior we could not catch any issues w.r.t power and ground from gate level simulation. if you look at the verilog model above, “else will never get executed at all”
It took some time to figure out that supply statements are causing this behavior. Again this shows the significance of running sign-off MV checks for detecting MV related issues.
- Godwin Maben