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Low Power Sessions at SNUG San Jose 2009

Low Power Sessions at SNUG San Jose 2009:

This year at SNUG San Jose, there are many sessions related to Power.


(1) A Predictable Approach to Reducing Clock-Tree Power using IC Compiler Low-Power CTS

(2) Techniques for Achieving Higher Completion and Verifying Low Power Designs in Formality

(3) Low Power Design Methodologies; Design for Power Gating – And What UPF Can, and Cannot, Do for You

(4) VMM – Low Power

(5) Leakage Power Optimization : An Improved Synthesis Methodology

(6) Power Rail Noise Minimization for EMC-Aware Design

(7) Using ESP-CV for Dynamic Power Analysis of Custom Macros to Reduce Analysis Time and Improve Accuracy

(8) Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP

(9) Power-Aware Test: A Burning Issue?

(10) Galaxy Test: Power-Aware DFT/ATPG and Technical Updates

(11) Multi-Voltage Implementation Methodology Using UPF


Schedule/Abstract for each session at SNUG San Jose is available at the following link

SNUG San Jose Schedule

SNUG San Jose Session Abstracts


Hope to meet you at one of these sessions.


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