Today let’s look at the various structural errors or bugs that can be really destructive for any MV design. Structural error is a bug, which is caused either by, the way RTL is written or implementation tools interpreting the power intent incorrectly. These can be further classified as structural errors leading to electrical violations or […]
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Its been quite some time since I blogged , I was on a vacation for last 3-4 weeks. Nice to be back again. For next few posts, planning to talk through the verification challenges seen on a low power design. First let’s try to classify various types of bugs that can be found in a […]
Posted in low power general | Comments Off on Low Power Verification
I have worked in the VLSI industry for 14 years as a digital IC designer. My recent work has been focused on low-power challenges associated with multi-voltage/- Godwin Maben