Magic Blue Smoke


Polling Low Power Design Styles

Based on my interactions with many designers for the past few years, most common
techniques in practice/proven today are

(1) Power Gating (Majority)
(2) Static Multi-VOltage
(3) Dynamic Voltage Scaling
(4) Adaptive Voltage Scaling
(5) Back Biasing

But lately I am hearing about new techniques being tried to prepare for future technologies, some of them include

(a) Razor
(b) Vanilla Flavor of Asynchronous Design
(c) Source Biasing
(d) DVFS to meet performance requirement at 45 and below
(e) Useful Variation
(f) On-Chip Process Monitor, to adapt to varying PVT
(g) Active Leakage Power Reduction(dynamic power cutoff)

I would like poll our low power user community on how many of you are really looking at
validating any or all of the above?