Magic Blue Smoke

 

UPF Synthesis Script

Hello all,
My apologies for being inactive for last 4 weeks, I was bit busy. As per many request, here is a sample synthesis script for UPF flow……

Please note that, some of the commands used here may not be very specific to UPF, but good to have for better power optimization(for example reading vectors)

############# Script: compile.tcl ####################
############## Date : 7/08/2007 ####################
############## Author: Godwin Maben ####################

create_mw_lib -tech $mw_tech_file $dir_name
set_mw_lib_reference -mw_reference_library $mw_reference_library $dir_name
open_mw_lib $dir_name

############### Read the Verilog RTL files #######################
analyze -format verilog [ glob rtl/*.v]
set_clock_gating_style -sequential_cell latch
-minimum_bitwidth 2
-num_stage 2
-positive_edge_logic {integrated}
-neg {integrated}
-control_point before
-control_signal scan_enable

elaborate lvds_system
current_design lvds_system

link

set_tlu_plus_files -max_tluplus ./tech_file/maxtluplus.tluplus -tech2itf_map ./tech_file/tech.map

set mv_insert_level_shifter_verbose true

####### Load UPF ######################################
load_upf power_intent/lvds_system.upf

################# Source the SDC constraints #######################
source -echo ./sdc/lvds_system.sdc

##### Set the right operating conditions ###############################
set_operating_conditions -max WCCOM
set_voltage 1.08 -obj {VDD_HIGH VDD_HIGH_CRC_VIRTUAL }
set_voltage 0 -object_list {VSS}
set_voltage 0.864 -object_list {VDD_LOW VDD_LOW_RX_VIRTUAL}
###########################################################
set_fix_multiple_port_nets -all -buffer_constants

extract_physical_constraints -verbose ./def/fp.def -output $NetlistDir/fp_place.tcl

create_voltage_area -coordinate {14.835 62.195 41.045 105.375 } -power_domain TX_AON
create_voltage_area -coordinate {46.425 47.875 79.385 99.97 46.425 47.84 111.41 47.875 12.53 15.115 111.41 47.84 } -power_domain CRC_GEN
create_voltage_area -coordinate {81.745 65.695 110.245 105.455 } -power_domain RECIEVER

set ptpx_map_name rtl_verilog_POWER_SYNTHESIS_map_ptpx.tcl
read_saif -input verification/dump/rtl_verilog.saif -instance tb/lvds_system
compile_ultra -timing -scan -no_autoungroup -no_seq_output_inversion -gate_clock

## Write out reports as well as Verilog/MW database for later use ###
change_names -rule verilog -hier
write -f verilog -h -out ./$NetlistDir/compile.v
write -f ddc -h -out ./$NetlistDir/compile.ddc
write_sdc -nosplit ./$NetlistDir/compile.sdc
write_link -nosplit -out ./$NetlistDir/compile.link
save_upf $NetlistDir/compile.upf

############# Insert DFT Logic ##############################
source -e scripts/dft.tcl

check_mv_design -verbose
change_names -rule verilog -hier
write_milkyway -out dft -over
get_always_on_logic -all
get_always_on_logic -cell

report_hier -nosplit -noleaf > $ReportDir/hier.rpt
report_timing -att -net -trans -cap -input -volt -nosplit > $ReportDir/timing.rpt
report_power -hier -hier_level 1 -verb > $ReportDir/power.rpt
write -f ddc -h -out ./$NetlistDir/dft.ddc
write -f verilog -h -out ./$NetlistDir/dft.v
save_upf $NetlistDir/dft.upf
exit