Magic Blue Smoke

 

Functional Simulation using UPF (Cont’d)

Last week we saw how UPF is written from verification perspective and today lets see what information from simulator will help debug the issues.

First lets look at some of the information printed out by simulator when UPF is enabled.

Automatic Assertions Synthesized:

(1) INFO : Sleep Signal value changed. SleepSignal SLEEP corresponding to signal ‘testbench.dut.PwrCtrl.SLEEP’ changed to value = 1 at time =1094000

The above assertion informs user that Sleep signal named “SLEEP” responsible for shutting down block has wiggled.

(2) INFO : Design state changed. Design transitioned from BOOT state to DMA state at time 1094000.

Above assertion informs user that state of the design has changed, this state change is based on the change in voltage on rails and its per information described in UPF given below

add_port_state VDD_HIGH -state {HVoltage 1.08}
add_port_state VDD_LOW -state {LVoltage 0.864}
add_port_state crc_sw/out -state {HVoltage 1.08} -state {CRC_OFF 0.0}
add_port_state rx_sw/out -state {LVoltage 0.864} -state {RX_OFF 0.0}

create_pst System_State -supplies {VDD_HIGH VDD_LOW VDD_HIGH_VIRTUAL VDD_LOW_VIRTUAL}
add_pst_state BOOT -pst System_State -state { HVoltage LVoltage CRC_OFF RX_OFF}
add_pst_state DMA -pst System_State -state { HVoltage LVoltage HighVoltage RX_OFF}

Corresponding Waveform for the above state change is shown in the picture below

Voltage Aware Functional Simulation Waveform

(3) WARNING : Corrupting Island’s retained registers.
Retained registers of island Shut_Down_Hibernate have been corrupted because Retention Rail value has fallen below threshold value at time = 3818000

Above assertion warns user that, simulator corrupted the retention register, as voltage to these fell below the value specfied in the UPF.

Many more assertions similar to what’s shown above is synthesized automatically by VCS while simulating the design in UPF mode.

As you see from the above explanation, Voltage is no longer treated as Binary 1’s and 0’s instead real transient voltage is considered during functional simulation