Magic Blue Smoke

 

Functional Simulation using UPF (Cont’d)

Last week we discussed the various ways UPF can be used to model functional behaviour of a Mult-Voltage/Power Gating design. This week lets look at the following:

(1) Voltage ramps, and
(2) How will the simulator flag a violation, when some activity is triggered during the ramping up cycle or ramping down cycle?
(3) How to Model Voltage Regulator?

(1) Voltage Ramps and Modelling Voltage regulator:

One of the main requirements during functional simulation is to monitor signal ramps. For example, during shut-down and wake-up of a block, it takes some time for the power network to stablize with the required voltage. Now, if we don’t model this, the simulator will not validate the signal interaction with respect to change in voltage. This might lead to missing some functional bugs such as:

(a) Submitting request by an already powered block to a powering up block
(b) Assuming Always-on block to operate properly, while other blocks in the design are waking up and disrupt the current distribution to the block under question.
(c) ……etc

Now, in order to accomplish this, we need to define the voltage ramp using the verification methodology of VCS as shown below:

Vdd.legalvalues = {0-0.864};
Vdd.value = “tb.regulator_0.Vdd”;
VDD_memory_32kx8.legalvalues = {0-1.08};
VDD_memory_32kx8.value = “tb.regulator_1.VDD”;

If you look at the above format, it clearly shows that we are defining the voltage range of the signals supplied through regulators named regulator_0/regulator_1. These VDDs are associated with their respective blocks through UPF as described in the previous post.

The next step is to define the standby voltage value as well as shut-down values, as given below:

memory_32kx8.driving = VDD_memory_32kx8;
memory_32kx8.sleepheader = tb/system_controller/power_sequence/power_down;
memory_32kx8.sleepheaderthreshold = 0.0;
memory_32kx8.standbyvalues = {0.6};
memory_32kx8.shutdownvalue = 0.0;

From the above description, we are telling the simulator about the “power_down” signal, Standby Voltage value(0.6) and the voltage value when the block is shut-down.

So when you simulate the design using VCS along with UPF, simulator will make sure that these values are kept in mind while simulating the design. The above behaviour is shown in waveform captured below:

voltage_aware_waveform_02.jpg

In the next post, lets see how the simulator flags user about illegal states or behaviour with respect to change in voltage.

Before I sign-off for today, I would like to take a quick suvey on how many designers want to know a methodology to implement and verify design using Back-Biasing/Source-Biasing? Since I am getting many requests on the same, if you can just fill out the form below saying YES/NO, it would be really helpfull for me to work on this topic as well.

Link to Survey(Two questions only with Yes/No as options)
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Do you use Well Biasing in your design ?
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