Posted by Godwin Maben on January 10, 2008
One of the main advantages of using UPF is that it ensures that the low power nature of a design is taken into account during functional verification. If we look at the various factors that need to be validated in the RTL functional simulation w.r.t Low Power Techniques, here are some of them:-
(a) Functional Correctness of all the signals, when voltage is varying.
(b) When a block is shut-down, how will the outputs of this block be treated ?
(c) When a block wakes up, is the neighbouring block expecting/sending some signals to the block waking up, during ramp-up time ?
(d) Is the signal properly recieved by the block, which is still waking up?
(e) How to simulate Switch Behaviour as well as Power Acknowledge?
(f) Does the Voltage level through LS/ISO cells actually shift the voltage ?
(g) How do we save certain flop states, when a block is powered down?
(h) Did we restore the flop states properly after wake-up ?
(i) How to simulate data corruption of retention flops, when the voltage on the retention power is below the required value?
Now let us take a look at the various UPF constructs, which enable us to verify some of the above.
List of UPF constructs, which are useful for functional validation:-
I think for today, this is quite a bit of data ! In my next post, I will continue on the simulation aspects using UPF.
- Godwin Maben