Posted by Godwin Maben on October 15, 2007
Most common issue faced in any Low Power Design is how can we minimize noise coupling between different rails and between cells in the same power domain. I am planning on discussing these in my next 2 posts.
Power and Ground Noise can degrade timing and can lead to functional failures. Most commonly used method is to insert decoupling capacitors to minimize the IR-Drop issues. Insertion of these Decap cells can be more challenging in a Power Gated design than a normal design. One of the reason for this being more challenging is “In Rush current management“.
In any power gated design one of the main requirement is to make sure that block that’s being shut-down wakes up as quickly as possible, without impacting the functionality of the other alive blocks. But this requires a very well managed In-Rush current circuitry. Now the question is , how come this impacts Decap Insertion?
If we remember, one of the most common methodology to minimize Current Surge during wakeup is
(1) Hook up the switches in Daisy Chain fashion
(2) Hook up the switches in buffered fashion
(3) Hook up the switches in Star Topology….etc
Now main goal in the daisy-chain topology is to sequentially charge the power gated block to reduce the current surge. However the current required to turn on the first switch of each chain can cause significant noise and voltage drop to the neighbouring cells. So one of the basic thing we need to follow is insert Decap’s next to switch cells, which is the main source of noise during wake-up.
But blindly inserting lots of decap’s in a power gated design has its own implication, which I will try to cover in my next post.
- Godwin Maben