Magic Blue Smoke

 

How to model Special Cells in libraries?

I have been post-poning explaining about the library requirements for quite sometime. Today let me explain little bit on library modelling of special cells such as

(1) Level Shifter
(2) Isolation Cell
(3) Retention flop
(4) Always On Cell
(5) Switch

Most important information to note here is, these special cells may have multiple power pins and hence we have to describe these models with pg_pin so that the timing arc’s are w.r.t to these power and ground pins as well

(1) Level Shifter:

cell (low2high_ls) {
level_shifter_type : LH;
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
std_cell_main_rail : true;
}
pg_pin(VDDL) {
voltage_name : VDDL;
pg_type : primary_power;
}
  is_level_shifter : true;
  pin(I)  {
    direction : input;
    capacitance : 0.0034;
    rise_capacitance : 0.0032;
    fall_capacitance : 0.0034;
input_signal_level : VDDL;
related_power_pin : VDDL;
related_ground_pin : VSS;
  }
¼br>   pin(Z)  {
    direction : output;
output_signal_level : VDD;
related_power_pin : VDD;
related_ground_pin : VSS;
…..
}

(3) Retention Flop:

cell (retention_flop) {
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin (VDD_retain) {
voltage_name : VDD_retain;
pg_type : backup_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}

……..

cell_footprint : “retention_flop” ;
  power_gating_cell : “retention_flop” ;
  ff(“IQ”,”IQN”) {
    next_state : “((D !SE) + (SE SI)) (wakeup !sleep)”;
    clocked_on : “CP”;
  }
pin(wakeup)  {
always_on : true;
    direction : input;
    capacitance : 0.0012;
    rise_capacitance : 0.0012;
    fall_capacitance : 0.0012;
    power_gating_pin (“power_pin_1”, 1);
……

}

(4) Always on Buffer:
cell (always_on_buffer) {
always_on : true;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin (VDD_retain) {
voltage_name : VDD_retain;
pg_type : backup_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
……….
}

(5) Switch Cell:
cell (header_switch) {
switch_cell_type : coarse_grain;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
direction : input;
}
pg_pin(VDD_internal) {
voltage_name : VDD_internal;
pg_type : internal_power;
switch_function : “sleepin”;
pg_function : “VDD”;
direction : output;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
direction : input;
}

……

pin(sleepin)  {
switch_pin : true;
always_on : true;
    direction : input;
    capacitance : 0.0046;
    rise_capacitance : 0.0046;
    fall_capacitance : 0.0046;
  }

pin(sleepout)  {
power_down_function : “!VDD + VSS”;
    direction : output;
    max_capacitance : 0.1694;
    function : “sleepin”;

…..

}

If the required attributes highlighted in the above .lib model is present, most of the tools will be able to identify them as special cells and optimize them accordingly.