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Retention Mechanisms used in a Power Gated Design (Cont’d)

In the last 2 posts, we discussed how retentions cells look like and what are the advantages/disadvantages. Since most of the designs do have memories and they tend to be shut-down, how is the state of memory retained ? We cannot reload the data from external memory into the local memory. Today let’s see how this is accomplished.

Fifos and Stacks are often flushed before powering down the device and caches are initialized once the device wakes up from shut-down state. In these scenarios, we can power down the memories to save static power by sacrificing memory data.

However, for high performance designs which require fast wakeup, the contents of on-chip memory need to be retained during shut-down. Various memory retention mechanisms are in use today.

The fundamental requirement is to save as much leakage as possible without corrupting the data.

It is not feasible to introduce a retention circuit like those discussed in my previous posts for memory cells. Any such circuit will cause an unacceptable area increase. Instead various retention schemes such as VDD/VSS save_restore and Source/Drain diode bias save_restore mechanisms are used.

VDD/VSS save_restore Mechanism:

In this method, a separate power supply is provided to memory, which will be lowered to a voltage closer to Vt(0.4-0.5V) during shut-down.

Source Biasing save_restore Mechanism:

The principle of the source biasing save_restore mechanism is to apply reverse body bias for further leakage reduction after lowering the memory operating voltage.

In this method a Diode is inserted in the source supply path of the memory array and this diode is controlled through a switch.

In normal operation the sleep signal is deasserted, hence the diode is bypassed as the switch is closed and works like a regular power supply. In shut-down mode switch is open and hence the source supply to the memory cell is through the Diode. The built-in threshold voltage of the diode rises the ground voltage closer to Vt and hence the leakage is reduced, similar to VDD save_restore mechanism.

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