Magic Blue Smoke

 

Retention Mechanisms used in a Power Gated Design

Again coming back from last week’s training, there were some pressing concerns that led me to write a short note.

(1) How can we retain state of some of the registers in the design?
(2) How to deal with memory state?

Let me try to explain each one of them based on last 2 design experience.

For regular logic blocks, there are multiple ways to wake-up fast without losing much of information.

(a) Use retention flops to save state of some important registers. For example state of control block, which forms the heart of the whole system.
(b) If chip is aimed at At-Speed testing, scan chains of the design can be used to scan out the data to an external memory and scan in after wake-up. This may not be as fast as using retention flops.
(c)….. there are many more possible methods.

Again w.r.t to retention flops there were questions about

(a) How many type of retention flops are available.

I have seen 3 types.
(1) Single save/restore pin retention latch (Slave latch being always on)
(2) Single pin Baloon Latch
(3) Dual Pin Baloon Latch

Let’s talk about the pro’s and con’s of these and also on memory retention in my next post.

please fill in if anyone has seen different ways of retention mechanism/retention flop types.