Posted by Godwin Maben on July 9, 2007
In the last few trainings I attended, most common question on everyone’s mind were
Can you list out at a higher level the challenges of implementating power gating . Thought of listing them here
(1) Design of the power switching Structure
(2) Design of the power/sleep control blocks
(3) Selection and use of retention registers and isolation cells. Trade-off between retention flops Vs cost/timing/wakeup.
(4) Minimizing the impact of power gating on timing and area.
(5) The functional control of clocks and resets
(6) Interface isolation
(7) Developing the correct constraints for implementation and analysis
(8) Performing state-dependent verification for each supported power state
(9) Performing power state transition verification to ensure all legal state entry and exit arcs are simulated and verified
(10) Developing a strategy for manufacturing and production test
Guys who have designed a chip with power gating, can you list out some of them If i missed any in the above list!
- Godwin Maben