Posted by Godwin Maben on June 18, 2007
Finally I am back from very long business trip.During my trip, I got a chance to interact with many designers, who are about to start designing chips with MV/MTCMOS in mind. The most common concern everyone had before starting to implement the design are
(1) How much Leakage Power Can I save if I use MTCMOS design style? Is there an alternative/substitute for the same?
(2) Is the power saved worth the effort put in to incorporate the changes in the design methodology?
(3) How will my new sign-off flow look like ? Is it robust enough to sign-off the design satisfying all the requirements ?
(4) Low Power Verification: Is there a well defined methodology to verify the design’s functionality given MTCMOS design style needs robust verification methodology?
(5) How do I decide on whether to use Header or Footer ?
(6) How important is Dynamic IR drop? Is this required even if I am designing my chip at 130nm?
(7) How good are the current EDA tools to accomodate all the requirements generated from the various low power design style such as MTCMOS/VTCMOS/MV….etc?
Hope to hear back from everyone on thier questions/concerns/answers to the above questions if some one has already decided on any of the above.
- Godwin Maben