Posted by Godwin Maben on May 9, 2007
Guys, I really apologise for not updating my blog more frequently. Next 2 weeks I will be away on a business trip, will try to post atleast a couple of times.
Today let’s look at the modelling of logical library cells specifically for MV. Accurate modelling of libraries is one of the crucial requirement for any design as we are going to sign-off using these libraries.
(1) Modelling of regular Std Cell library.
Traditionally this used to be very straight forward. But with MV, there are a couple of questions that need to be addressed:
(a) Standard cell for different Voltages
(b) What’s the derating model used? K-Factor based is not recommended due to lack of accuracy.
(c) One of the reason why this is so important is, if we are running IR Drop based Static Timing Analysis, how will my timing be derated ?For example cell is characterized at 0.9V, but if the Voltage at the cell in question is 0.82V, how will this be timed?
(d) IMHO, the timing accuracy is not very reliable if IR-Drop is more than 5%, if regular NLDM models are used.
(e) I would look at more options available today in terms of modelling libraries for better accuracy. One such option would be to move towards CCS timing/power models, rather than traditional NLDM models.
(f) IMHO, we should also include power/ground pins in the logical libraries. I will talk about the reasoning behind this in the later blogs.
Let me discuss modelling of other library cells in my next post. Guys jump in and throw in your questions/thoughts.
- Godwin Maben