Posted by Godwin Maben on May 2, 2007
Wow, Again its been a while since i updated my blog. I have been very busy lately due to multiple tape-out related activities.
Let me continue from where I left off last time.
Questions were how do we simulate:
(1) Power Switch Behaviour
(2) Isolation Behaviour
(3) Level Shifter Behaviour
(4) Retention flop.
Remember, we dont have any representation of the above cells in the RTL. Firstly do we need to simulate the behaviour of all of them ?
Typically in good old days, PLI’s were written by verification teams to simulate all of them. For example say,
Power Switch Behaviour:
We can write a function/pli with following specification
$power(block_to_be_pd, type_of_pd(aon/shut-down)signal_used_for_shut_down(switch_enable), acknowledge signal(acknowledge))
Now this PLI should look at the “type_of_pd“, which is either always_on or shut-down and act accordingly. In case block under consideration is of type shut-down, then whenever it detects an activity on the “switch_enable” signal, it should corrupt all the signals of the block. Once all the signals are corrupted, it should generate an “acknowledge” signal after a user specified delta delay.
IMHO, this should also include something like:
This enables us to simulate the behaviour of power sequencing. There is lot more that can be added to this PLI routine such as:
(1) Trace through the fanout of all the outputs of this block. Flag an Error if corrupted signals are propagated till the reciever.
(2) When switch_enable goes inactive, either reset all the logic in the block to “X” or to some random pattern.
(3) During power up, stagger the power up of different blocks randomly!!!
(4) Emulate Impact of IR-drop using staggering principle!
This is again pretty straight-forward. All we need is a PLI or a simple function in Verilog, which will be something like:
If “early_switch_enable” is active, maintain the output at “output_sense(1/0)” value, irrespective of the state of input.
This is again pretty straight-forward from a simulation perspective. The PLI or a simple function, which will be something like:
Whenever “early_early_switch_enable” is active, copy the contents of “register_names” onto a local shadow_register or a local memory, and whenever “wake_up” goes active, reload the “register_names” with contents of the shadow_register.
Now there are various complex flavors of all the above depending the circuit behaviour of these speciall cells.
The major question to be answered is, are we looking at 2 different RTL? One for synthesis without any PLIs and one for simulation with PLIs. Can these PLIs be synthesized into H/W automatically by all the EDA tools available? Is this the right approach?
Can these be solved using a different approach? That’s where the UPF(Unified Power Standard) standard helps in describing the power intent of the design to both the implementation tool and the verification tool in similar way.
In UPF, the above 3 types of behavior can be represented using following constructs:
And all the above UPF constructs are simulatable as well as synthesizable.
- Godwin Maben