Magic Blue Smoke


RTL Implementation and Functional Verification of MV design – Part II

Now, if we look at the questions we had in the last blogpost, some are very design specific. Let me try to put across my view for the same.

 RTL/Micro-Architecture requirements in detail

(1) Some of the blocks will be shut-down. Does your design have control logic that generates signals locally to shut-down the block ?

I think, if the design was architected from the beginning with power gating design style in mind, it will have a control block, which probably might make decisions on which blocks to shut-down and when and how long this has to be shut-down….etc. Now the other question that comes to mind is : Is this sufficient? Do I need a separate power control block, which takes inputs from the control logic and generates the power down signals in the desired sequence ? I think it’s a good practice to introduce such logic to control the complete power-down/power-on sequence.

(2) Lets look at the control signals required:

           (a) Control Signal for the Power Switch (Switch_enable)
           (b) Control Signal for the Isolation Cell Enable (Isolate_enable)
           (c) Control Signal for the retention flops (Save_Restore)

Now, I think ideally all these control signals are derivative of each other!. Its just that these signals need to be generated in the right order for the circuit to behave as desired. Here is one snap-shot of the waveform that generates these signals.

                        “Power-Down Sequence”


                           “Power-Up Sequence”


I would assume, for power down one of the correct sequence could be:-

@ Inactivity generate
 (1) Generate Save_Restore: This will indicate that the retention flops needs to transfer the contents from Master Latch to Slave and go into sleep mode.
 (2) Generate Isolate_enable: This will enable isolation cells to be active and clamp the output to a known voltage and state.
 (3) Since all the basic elements are informed of the shut-down operation, we can now generate Switch_enable, to turn off the power rails, that control specific blocks.
 (4) There could be other actions such as reduce the frequency/reduce the voltage….etc as a part of this sequencing.

As a part of this sequence definition, we should define the right Assertions too, so that if the right sequence is violated, this can be flagged up-front.

Sequence power_sequence;
Save_Restore && Isolate_enable && Switch_enable ==0
##1 Save_restore ==1
##1 Save_restore && Isolate_enable == 1;
##1 Save_restore && Isolate_enable && Switch_enable ==1;

(3) If the above control signals exist in RTL, these are driven by power management logic but are not connected to anything!

Even though as said in point (2) these control signals are generated by Control Logic, these are not connected to anything outside this control logic. The reasons are:-

 (a) Power Switch that’s used to cut-off power does not exist in RTL. These get added probably during Power Planning. Floor-planning/Power Planning Engineer will add these based on the specification from the Architect of the chip. Till switches are in place Switch_enable is floating.

 (b) In RTL there is nothing specifically done for Retention Flop, these are coded like any other register and Synthesis tool will infer them based on some commands. Save_restore end up floating.

 (c) Isolation cells does not exist in the RTL and hence Isolate_enable is floating.

Now the question is how should we simulate them?

Let’s look at some of the possible answers in the next blogpost. Till then I hope to receive more feedback from my readers regarding the challenges they face in Power Gating design.