RTL Implementation and Functional Verification of MV design – Part I

Well, I was very very busy these days so could not catch up with my blog. Today let’s talk about RTL in a Mult-Voltage environment and it’s implication on verification.

In  the earlier blogs we discussed MV design infrastructure. Today let’s look at ‘Power Gating’, the most common design style to reduce Leakage Power. Typical characteristics of this design style are:-

(1) Some of blocks in the design will be shut-down, when not functional.
(2) There will be blocks, which are always on.
(3) These blocks could be of same voltage or different voltage.
(4) The power structure to shut-down a block could be either completely external or internal. Most commonly used is internal power structure to shut-down blocks.
(5) Either VDD or Ground can be cut-off.

Consider a classical scenario, wherein implementation/verification becomes a real challenge.

“We have a chip taped-out, working fine in 90nm. We want to add more functionality to the same chip and want to accomdate the logic within same die-area as before. To accomdate this silicon real estate requirement, we decided to move to 65nm. Since the application as well as the technology node demands extremely low leakage, we want to shut-down some blocks in the design.”

Given this, it’s very very challenging to accomodate Power Gating, since this chip is not architected to accomodate Power Gating

Now, given the characteristics of Power Gating Design Style, here are some facts I think, we need to consider while Micro-Architecting the design.

RTL/Micro-Architecture requirements:-

(1) Some of the blocks will be shut-down. Does your design have control logic that generates signals locally to shut-down the block ?

(2) Lets look at the control signals required:
           (a) Control Signal for the Power Switch (Switch_enable)
           (b) Control Signal for the Isolation Cell Enable (Isolate_enable)
           (c) Control Signal for the retention flops (Save_Restore)

(3) If the above control signals exist in RTL, these are driven by power management logic but are not connected to anything!

(4) Is a proper sequence for all the control signals defined ? Examples of this could be:
        Switch_enable @ 5ns
        Isolate_enable @ Switch_enable “+” 10ns
        Save_Restore @ Isolate_enable “+” 20ns

(5) Now the block, which we are trying to shut-down needs to generate an Acknowledgement signal, indicating power-up or power-down. This signal is again a floating output not driven by any logic,but is processed by the power management logic!!!

(6) Is there a requirement, such as : Block needs to be powered-up within “n” clock cycles? What if you dont recieve an Acknowledge within “n” clock cycles?

• (7) If all the above are taken care of during micro-architecting, there are still few more questions that need to be answered for Logic Synthesis and Functional Simulation:
   — Is Isolation Cell/Level Shifter part of your RTL ? How are you coding this ? Are you instantiating it in the RTL?
   — Are Retention Flops part of RTL ? How are you coding this ? Are you instantiating it in RTL ?
   — How will the control signal get interpreted by the implementation tool, as they (the control signals) are floating?
   — How will Acknowledge signal get generated? Since it’s required by power management logic, but is not generated by any hardware?
   — How will functionality of all these get verified, given that some of them are either floating or not generated ?
   — How will the shut-down get simulated ? Nothing special is done in RTL to simulate this behaviour.
   — How do we model Shut-Down to verify the functionality?
   — How will the retention flop behaviour get simulated ? In RTL it’s coded like any other register.
   — When a block wakes up from shut-down, what should be the status of all the logic? Is random better or using “X” better ? Wouldn’t “X” be very pessimistic ?
   — How to simulate the behaviour of “n” clock cycle requirement of the Acknowledge Signal from power-down block ?
   — If there are some always on logic residing in a shut-down block, how do we implement them? How do we verify them ?

Well, I think that’s a lot of questions for today. Guys, jump in and add more questions that you have come across during MV design implementation. In the next section, I will discuss my views and some good practices to address all the above questions efficiently.