Before we start looking at implementing a Multi-Voltage design there are certain questions we need to find out from process/library perspective such as
Available Operating Voltages(PVT)
Do we have special cells such as Level Shifters/Isolation cells/Power Gating Switches ?
If Level Shifter exists, what kind of level shifters are available? (ex: Enable Level Shifter..etc)
What are the different corners that need to be used for sign-off?
How should we handle OCV?
How accurate are these timing models? Is NLDM good enough or do we need CCS/ECSM models?
Do we have special cells with Dual Rails(ex: Retention Flops)? If yes How is the timing captured for each rails?
Are these cells characterized for Power, do they have State Dependent Path Dependent Information?
If special cells exists, is it modelled according to EDA tools requirement?
For Feed through implementation, do we have special Always On Buffers ? What’s the impact of routing the secondary power pins of these buffers on routing resources?
Given range of Operating Voltages, is there an easy way at early stage of implementation cycle to judge on right Voltage selection? (power/performance product)
Am I getting required power savings by implementing the design in Multi-Voltage style? For ex. If number of special cells required to implement this are too many, is it worth the effort? Can we look at an alternate way of saving power?
Just to give an example , recently for one design I found out that around 26K Level Shifters were required to implement a block and this has an adverse effect on power. But we did not have a choice as this was the best possible Voltage that met the required timing/power specification.