Magic Blue Smoke

 

New Problem in the Block

Hi, my name is Godwin Maben; I have been working with customers in trying to understand their low power concerns since last 6 years. Interesting thing to note is that low power concerns have become more of a main stream problem as opposed to secondary in the last 6/12 months. An interesting thought occurred to me, why not create a community, where in we all can exchange some ideas to solve low power problems and educate/share knowledge about various techniques used today and their challenges through out the flow.

Hopefully it’s going to be very a useful media to exchange ideas as well as creating a low power community to solve/exchange design/verification problem related to low power.The question that needs to be answered is How come all of a sudden Power has become a major concern and is something which cannot be overlooked nor ignored.

I would put them in the following 2 categories.

  •  Process Nodes:90/65/45nm (Shrinking Device size)
  •  Yield Loss due to increasing Process Variation (includes impact on Vt)

Before we get into too many details about why/what/how/when, let’s try to understand few basic questions about power

Here is a link, which gives insight into some of the basic concepts for Power

http://www.reed-electronics.com/semiconductor/article/CA6375404

Now let’s look at the factors influencing these components of Power.

How can we reduce Dynamic Power? Is everything under designer’s control?

 Well, as implied by the equation 0.5C*V*V*F

(a) Reduce C
(b) Reduce V
(c) Reduce Frequency/Activities

I think all the above is definitely under designer’s control and can be tackled using different techniques.

How can we reduce Leakage Power?

This is a tricky one as it lot depends on the process; Designer’s can try minimizing it, but not completely controlling it.

 Graph Below shows the ITRS data on leakage power trends.

picture1.jpg

Let’s talk/discuss about these topics in my next session.