Magic Blue Smoke

 

Low Power Standardization

Any design house implementing low-power ICs require a standard for describing low-power design requirements. To achieve the required power targets, design teams are increasingly adopting advanced power management techniques such as Multi-Voltage, Power Gating, Well biasing….etc. Such techniques if implemented quadruples design implementation effort and increase the risk equally. Given this the ideal way to reduce the risk is to introduce a standard that describes power intent of the designer, which can be used both by the implementation and verification team.

I found an interesting article, which talks about  requirements for power standardization.

 Low Power Standardization

Now since UPF 1.0 is already approved by Accelara, some questions that comes to my mind,for Power Gating Implementation, can UPF help us in verifying/implementing the following tasks

  • Will the Shut-Down Blocks affect the functionality of Alive Blocks ?
  • Did the retention register save the states properly when block was shut-down?
  • How do I verify the shut-down/wake-up sequence?
  • How long does the block take to wake-up ?
  • Was Isolation cells inserted properly by implementation tools ?
  • Did Placement tools place any alive logic inside the shut-down block ?
  • Do I need Always On Buffers ?
  • What’s the impact of Voltage-Drop on Alive modules, when shut-down modules wake-up?
  • Since UPF is still an evolving standard, lets hope it answers all the questions that’s required to explain the power intent of the design