There seem to be some confusion about types of checks that need to be performed on a Low Power Design. In the Low Power static check world, following 3 types of analysis can be done on a design, in addition to various other checks.
How do we minimize or reduce area in a Low Power Design, especially when it come down to using special cells such as isolation cells, level shifter cells…etc
We are so much used to having explicit supply nets and ports in the design as well as in UPF, its hard to visualize how a hardware logic designer would code the UPF using supply sets. For those of you who are not familiar with supply sets, here is a quick preview of the same
Recently came across this request for clock gating retention latch. Here are some details on why these are required and what it means to the design.
Again sorry for the long break in writing, wish I could write at least one post per week,
There were many questions on why output isolation is preferred over input isolation logic, sorry could not get time to respond to all the queries related to this. Here is my view point on this
Sorry guys, got tied up with many projects and could not blog for almost 4 weeks.
- Godwin Maben