Magic Blue Smoke

  Often times many designers keep asking one question ; Does all EDA tools support UPF2.0 Commands. In theory all the commands in UPF are referred to as IEEE 1801 commands and all the supported commands by the tool can be accessed through solvnet article  (https://solvnet.synopsys.com/retrieve/021264.html) In my opinion in addition to the standard UPF […]

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There seem to be some confusion about types of checks that need to be performed on a Low Power Design. In the Low Power static check world, following 3 types of analysis can be done on a design, in addition to various other checks. (a) Critique Check     Power State Table is Golden here and […]

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How do we minimize or reduce area in a Low Power Design, especially when it come down to using special cells such as isolation cells, level shifter cells…etc Here is one scenario, where in “especially on a final sign-off netlist, can we get rid of these or will there be any electrical violations due to […]

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We are so much used to having explicit supply nets and ports in the design as well as in UPF,  its hard to visualize how a hardware logic designer would code the UPF using supply sets.   For those of you who are not familiar with supply sets, here is a quick preview of the same […]

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  Some interesting observation while running LVS on a power gated or a MV design. Here is quick preview on the problem description   As shown in the picture above if LVS is run on a Verilog netlist generated without bulk pin connections, bulk connections may not be correct from electrical perspective. More on how […]

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Recently came across this request for clock gating retention latch. Here are some details on why these are required and what it means to the design. Clock gating is the most common low power saving technique in use for a long time.  Latch based clock gating logic is typically used to avoid any glitches even […]

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  Monday, March 29, 2010 11:00 AM – 12:30 PM MA1 Tutorial : Implementation PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure MA2 User – Constraints and Power Challenges in Verification : Verification Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster Monday, March 29, 2010 1:45 […]

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Again sorry for the long break in writing, wish I could  write at least one post per week, Recently based on some silicon debugging, we realized verification did not cover some aspect of the power down function that lead to chip failure. Later realized that, this is  being mentioned some where in VMM LP manual, […]

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There were many questions on why output isolation is preferred over input isolation logic, sorry could not get time to respond to all the queries related to this. Here is my view point on this Output signal isolation method is usually a preferred choice than the input isolation method as former leads to fewer isolation […]

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Sorry guys, got tied up with many projects and could not blog for almost 4 weeks. I know we spend so much time in writing power intent of a design and validating whether its correct or not. In that process on a recent project, I did some analysis on how some of the intent generation […]

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