Looking Past the Horizon

Archive for the 'Uncategorized' Category

 

Is Synthesis Still Process-Independent?

Complex process and layout rules for finFET processes have a big impact on the decisions made during synthesis. For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion.

Continue Reading...

Posted in EDA, Electronic Design Automation, Uncategorized |

 

In-Design Rail Analysis Is A Beautiful Thing

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which brings me to the topic of power integrity and how to best build robustness into silicon – a very beautiful thing.

Continue Reading...

Posted in In-design Rail Analysis, Power Grid Optimization, Power Integrity and Reliability, Power Signoff, Thermal Analysis and Optimization, Uncategorized |