An often-overlooked cause of hold violations no longer can be ignored Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that. Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout. However, even after extensive signoff analysis, silicon failures still occur. The most critical and common silicon failures, the ones that need silicon re-spins to fix, are designs with hold violations. Some paths in silicon are just faster than signoff predicted, resulting in the chip being dead on arrival.
For more precise static timing analysis with less uncertainty, rethink the idea of timing models.
For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction was a crucial element of STA and more importantly, to the timing models that are required to perform the analysis. Having moved on from STA and into the world of Rs and Cs, I realized that parasitic extraction is without a doubt, one of the most interesting and under-appreciated topics in EDA.