Looking Past the Horizon

Archive for the 'Parasitic Extraction' Category

 

3D Extraction Necessities For 5nm And Below

For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more importantly, to the timing models that are required to perform the analysis. Having moved on from STA and into the world of Rs and Cs, I realized that parasitic extraction is without a doubt, one of the most interesting and under-appreciated topics in EDA.

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Posted in EDA, Electronic Design Automation, Parasitic Extraction, Static Timing Analysis |