Why the cloud is becoming necessary in complex designs. Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool suppliers to look more seriously into cloud-based solutions?
What moving to the latest transistor types will mean for IC designers.
Complex process and layout rules for finFET processes have a big impact on the decisions made during synthesis. For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion.
For more precise static timing analysis with less uncertainty, rethink the idea of timing models.
These Aren’t Your Fathers’ Design Flows
How machine learning can help meet PPA challenges and improve ECO optimization productivity.
For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction was a crucial element of STA and more importantly, to the timing models that are required to perform the analysis. Having moved on from STA and into the world of Rs and Cs, I realized that parasitic extraction is without a doubt, one of the most interesting and under-appreciated topics in EDA.