Looking Past the Horizon

Archive for the 'EDA' Category

 

MISing In Signoff

An often-overlooked cause of hold violations no longer can be ignored Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon failures still occur. The most critical and common silicon failures, the ones that need silicon re-spins to fix, are designs with hold violations. Some paths in silicon are just faster than signoff predicted, resulting in the chip being dead on arrival.

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Posted in EDA, Signoff, Static Timing Analysis |

 

Physical Verification In The Cloud

Why the cloud is becoming necessary in complex designs. Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool suppliers to look more seriously into cloud-based solutions?

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Posted in EDA, Electronic Design Automation |

 

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond

What moving to the latest transistor types will mean for IC designers.

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Posted in EDA, Electronic Design Automation |

 

It’s All About Staying Ahead of the Test Challenges Curve

As test pattern compression falls behind, new techniques are needed to keep test times in check. Since the early days when semiconductor devices contained a mere handful of gates, the manufacturing test world has been focused on how to detect the greatest number of potential defects in the shortest amount of time. This fundamental goal has not changed over the years and continues at 5nm and beyond.

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Posted in EDA, Test Automation |

 

Is Synthesis Still Process-Independent?

Complex process and layout rules for finFET processes have a big impact on the decisions made during synthesis. For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion.

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Posted in EDA, Electronic Design Automation, Uncategorized |

 

“Good Enough For Government Work?” Not Anymore.

For more precise static timing analysis with less uncertainty, rethink the idea of timing models.

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Posted in EDA, Electronic Design Automation, In-design Rail Analysis, Static Timing Analysis |

 

Design Flows At 5nm And Beyond

These Aren’t Your Fathers’ Design Flows

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Posted in EDA, Electronic Design Automation |

 

Regain Your Power With Machine Learning

How machine learning can help meet PPA challenges and improve ECO optimization productivity.

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Posted in EDA, Electronic Design Automation, Machine Learning, Sign-off |

 

3D Extraction Necessities For 5nm And Below

For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more importantly, to the timing models that are required to perform the analysis. Having moved on from STA and into the world of Rs and Cs, I realized that parasitic extraction is without a doubt, one of the most interesting and under-appreciated topics in EDA.

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Posted in EDA, Electronic Design Automation, Parasitic Extraction, Static Timing Analysis |