Posted by Jim McCanny on February 12, 2019
Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that. Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout. However, even after extensive signoff analysis, silicon failures still occur. The most critical and common silicon failures, the ones that need silicon re-spins to fix, are designs with hold violations. Some paths in silicon are just faster than signoff predicted, resulting in the chip being dead on arrival.
There are may possible reasons for hold time violations, such as process variation and crosstalk, both of which can lead to unexpectedly speeding up paths in the design. However, an often-overlooked effect is MIS, or Multiple Input Switching.
When multiple inputs to a cell or any cluster of transistors making up a logic function switch simultaneously they can speedup or slow down the switching of the cell output. The speedup effect is typically more pronounced with a 60% delay decrease not uncommon. Given than the delay of each cell or logic stage for the fastest paths contribute a larger percentage to the overall path delay, even a single stage with MIS can lead to a potential hold violation.
Difference MIS scenarios for a 3 input NAND
From the state table shown here there are times when this simple 3 input NAND gate can speed up or slow down with multiple inputs switching versus only one input switching. When there is a falling edge on I, J, and K at the same time, all the pmos transistors turn on at the same time. This causes the effective drive strength to go up. With the higher effective drive strength and the same capacitive load, you get a speed up in the output rising transition. Here you see a 2ps out of 5ps delay reduction. On the flip side, with all inputs rising at the same time, the net effect is a delay increase as the nmos transistors are trying to overcome all pmos transistors driving until the pmos devices completely turn off.
While traditionally static timing analysis and characterization tools have assumed single input switching, the good news is that Synopsys static timing signoff tools support MIS analysis without an additional characterization burden. For PrimeTime, the impact of MIS can be derived directly from the characterized CCS timing and CCS noise tables. In transistor level signoff with NanoTime, the impact can be incorporated directly into each stage simulation. In addition, in the same fashion as crosstalk delay analysis, timing windows can be used to exclude MIS effects that won’t occur due to the timing and logic relationships of the inputs.
The impact of arrival times on the MIP impact
For today’s high performance, highly optimized designs especially for regular structures like datapaths, register files and embedded memories, the impact of multiple input switching can no longer be ignored or simply margined. It’s essential that your signoff analysis flow is not missing MIS.
Thinking 2 steps ahead to address future challenges at 5nm and below.
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