Looking Past the Horizon

Archive for 2019

MISing In Signoff

An often-overlooked cause of hold violations no longer can be ignored Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon failures still occur. The most critical and common silicon failures, the ones that need silicon re-spins to fix, are designs with hold violations. Some paths in silicon are just faster than signoff predicted, resulting in the chip being dead on arrival.

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Posted in EDA, Signoff, Static Timing Analysis