Posted by Manoz Palaparthi on December 6, 2018
Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool suppliers to look more seriously into cloud-based solutions?
SoC designs continue to grow in both size and complexity every year. Today’s data-centric world demands chips that need to handle massive amounts of computations. The requirement to continuously add more compute power and new functionality is driving designers to move to the cutting edge of process technology in a short timeframe. These factors present a huge challenge for physical verification closure, especially as process technologies advance to 7nm, 5nm, and below. Physical verification is a compute-intensive task. A typical 7nm runset can have up to 10,000 complex rules, and about 100K DRC computational operations are required to implement these rules. As a result, full-chip DRC signoff at 7nm can take multiple days for a single iteration. Cloud computing is a promising approach to counter the runtime challenge for physical verification.
The next question – why now? A few years ago, using the cloud seemed scary. Semiconductor companies had several concerns about their designs in cloud – security of data, network latency, ecosystem support, and so on. Today, however, cloud solutions are openly embraced. As cloud adoption became the norm across other areas of our industry, we now feel more confident with offering IC Design in the cloud. Furthermore, all the pieces of the ecosystem are converging. Some EDA tools, such as Synopsys’ IC Validator, have evolved into full cloud-ready solutions. TSMC foundry recently launched “Open Innovation Platform Virtual Design Environment” (OIP VDE), a cloud design platform that allows TSMC customers to securely develop SoC design environments in the cloud. When I talked to several of my customers this year about their physical verification runtime concerns, most of them are eager to deploy their physical verification jobs in the cloud. They no longer hesitate to use cloud resources (as many as 1000+ CPUs in some cases), if it means full-chip DRC signoff can be done within hours instead of days.
Physical verification is one of the few design steps that is ideally suited for the cloud. Commands inside a runset are distributed into multiple parallel jobs that run independently on different CPU cores. The massively parallel distributed processing engine of IC Validator takes full advantage of the cloud’s flexibility and elasticity.
Looking forward, what are some of the new and exciting opportunities in this area? Machine learning, in concert with cloud computing, has the potential to bring significant value to design. For any ML application, building a large dataset to train the model is essential to improve the model’s ability to predict. Machine learning in EDA is starting to gain traction and lack of datasets is a key concern. The cloud gives us a chance to collect data in the right way, by aggregating only relevant data from the runs without giving away proprietary design information. It is also possible to group the datasets to tailor different approaches for different segments (e.g., all designers, or customers of a specific foundry, or designers within one company). Another advantage of design in the cloud is remote debugging; cloud design platforms such as TSMC’s VDE empower EDA tool suppliers to remotely and quickly debug customer issues.
Is now the time for IC Design and EDA to fully embrace cloud computing? The answer is a resounding “Yes!” Continued innovations will no doubt put cloud computing at the forefront of IC design in the coming years.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.