Posted by Taigon Song on December 6, 2018
What moving to the latest transistor types will mean for IC designers.
When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game in the industry. Not so long after, people started talking about FinFETs. All of a sudden, the hottest ICs in the industry were made out of latest FinFET technologies. Reminiscing from my undergrad till now, things here really moved fast. Nowadays, living inside the industry world, I hear that even FinFETs are expected to be out of the game soon. For example, they say FinFETs can’t be smaller than 5nm, but we’re already in 7nm processes. So, what’s next?
That’s why nanowire FET (NWFET), also called gate-all-around FETs, are gaining attention. First, it’s scalable beyond 5nm, and it’s better in terms of speed and power than FinFET. Better speed/power and smaller. Need I say more?
So, if I’m an IC designer, what’s going to be the change that’ll happen to me? The interesting part of NWFET is that it can be designed in two different styles – horizontal and vertical. The horizontal NWFET (h-NWFET) shares a rather similar design style as FinFETs. In the designer’s perspective, you just swap the fins inside a FinFET to nanowires and that’s it. Thus, if you’re a designer that has nothing to do with any devices, everything would be exactly the same when your design team decides to move on from FinFETs to h-NWFETs. Maybe the same PDK with some better transistor libraries and that’ll be it.
However, when your team decides to move to vertical NWFET (v-NWFET), things get trickier. V-NWFET lets transistors to be designed vertically. In other words, you can fill your silicon space with more transistors because v-NWFETs occupy less transistor space than any other transistor types. However, when I mentioned ‘trickier,’ I mean a paradigm shift in IC designs and for designers. For example, how will I design circuits out of these v-NWFETs? How about standard cells? What about SRAMs? This is because v-NWFET requires a totally different design style from any other circuit designs. Let me explain this difference by comparing a single inverter.
See how the footprint reduces 50%! Even the smallest standard cell area can be reduced to half when v-NWFET starts to be used. However, also note that the design style between h-NWFET and v-NWFET are totally different. Like the significant change between these two inverters, there would be a huge impact to all IC designs when v-NWFETs are introduced.
As a designer, I anticipate the migration to v-NWFET will be considered as a gigantic wave in the IC industry. First, every circuit design (I mean every!) is going to change. Standard cells, analog (e.g., PLL, ADC…), I/O, SRAM… We’ll need to re-design every circuit. This will take time, but it certainly will be worth it since it will lead to smaller footprint and silicon area (which is more money). Second, because the footprint reduces, parasitics of all these v-NWFET circuits would be smaller than any other previous non-v-NWFET circuits. This will lead to better circuit performance than any other transistors. Third, vertical transistors will lead to a new era of 3D ICs. While current technologies use TSVs (through-silicon vias) to stack one chip on the top of each other, v-NWFET proposes the possibility of transistors being designed on the top of another transistor. Research papers have already proposed the prototype of this amazing concept.
Anticipating v-NWFETs to be adopted in the near future, designers would need to re-think and validate their design flows to make sure everything is right. However, we are not fighting from scratch. For extraction, for example, Synopsys extraction technologies is the golden standard reference from device level analysis (Sentaurus TCAD) to 3D field solver (Raphael XT and QuickCap) and gate-level extraction (StarRC). Synopsys is heavily focusing on new technologies and is ready to provide a full solution when we decide to make this paradigm shift from FinFETs to NWFETs.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
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