Posted by Bernadette Mortell on September 20, 2018
For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion.
With the arrival of physical synthesis, physical effects could be taken into consideration in synthesis flows and front-end designers began asking what changes to expect when a new process node was released.
The benefits of physical synthesis are improved timing correlation based on actual physical information within synthesis including coarse placement and the floorplan. This added information in synthesis enables accurate timing estimates, allows the optimization engines to focus on the right paths and deliver better correlation and convergence throughout the flow. As physical synthesis has taken hold and became the mainstream synthesis flow, this significantly changed user expectations in several ways. Now users expect the quality of the output netlist will be better in terms of Performance, Power and Area (PPA) achieved. They expect it will be better suited to physical implementation in terms of reduced routing congestion using the placement seed provided by synthesis. And the correlation to results after placement optimization will be much tighter for timing, area, routing, and power. The handoff objective to place and route is to achieve better PPA and a convergent design flow. Ideally, the netlist handed off to the physical implementation teams should not come back to the RTL designer unless the actual design specifications have changed.
As FinFET process nodes have moved into mainstream production use, complex process and layout rules have a greater impact on the decisions made during synthesis. New choices for the synthesis solution and users to improve PPA include layer aware timing optimizations, performance and EM via pillar insertion, the use of non-default routing rules and special cells designed to improve metrics like pin accessibility at highly utilized regions. Physical synthesis now needs to understand the process technology parameters as well as the placement and routing rules to generate better netlist for physical implementation. As a result, physical synthesis needs to be aware of and operate differently when synthesizing for different process nodes.
Design Compiler Graphical feeds-forward design implementation guidance to drive the physical implementation flow that step-by-step converges on final PPA goals. The latest releases of Design Compiler Graphical can make tradeoffs between cells with better PPA characteristics vs. ones that are better for congestion and pin accessibility, assign nets to different routing layers to manage critical timing paths, add both electro-migration and performance vias, derive non-default routing rules and a myriad of other techniques to come up with a design which meets the required goals. When the design netlist and physical guidance is passed to the place and route tool, the resulting design PPA closely matches what the synthesis tool has predicted.
Starting at 7nm and continuing at smaller nodes, Design Compiler Graphical is validated by the silicon foundries for deployment readiness at each new process node. This means the synthesis tool has been enhanced to support the latest process rules, placement, routing, power and timing requirements and is aware-of and takes into consideration the physical effects of the new nodes.
So, getting back to the original question, does every advanced node design require this new flow where all the physical implementation factors are accounted for during synthesis? The answer is a resounding yes. For designs on the latest process nodes you will need to get used to updating the version of your tool and your synthesis flow/scripts for every new process node in order to achieve the best PPA and fastest convergence.
Goodbye process independence in synthesis, it was nice knowing you.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.