Posted by Mark Richards on May 14, 2018
These Aren’t Your Fathers’ Design Flows
It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40-nanometers was the most advanced node that I ever designed SoC’s at and, although it wasn’t easy back then, it pales against the myriad of challenges facing designers today.
Back then, compartmentalization of function and roles was relatively easy. We do design-planning and front-end design at the beginning, there is a blurry hand-off phase but then we happily go into back-end design and then we’re “relatively” done. We then do timing sign-off coupled with some remedial fixes for closure, a little bit of top-level re-optimization, final top-level closure, and then we’re off to the races. In the last few months of design it was more about thorough bug-hunting (hopefully negative; especially in your blocks!) but this period was also mostly focused on package signoff and cleanup. By this time, if you just did RTL coding, your life was a quiet one or more likely, you’ve moved on to the next chip.
Akin to introducing today’s 10-year-old kids to your 90-minute mix-tapes that you recorded off the radio to share with your friends, such a flow is now very much the vestige of a bygone era. What is most glaring however, is how different the latest demands already are and, as we project forward to 5-nm-and-beyond, how staggeringly different they are becoming for future nodes.
Margins are of course nothing new, but as processes have shrunk, the number and scope of them has increased. In their rawest sense, margins are, in the words of Donald Rumsfeld, the “known unknowns” and the “unknown unknowns”. These are the things that we either can’t or haven’t modeled in some effective way. Nonetheless they are needed to ensure the design is reliable, manufacturable and often just as important, implementable.
Process related margins have long been the target of innovation. As we progressed from flat margining, on-chip-variation (OCV) derates through to advanced OCV derates, and more recently parametric OCV derates, we have managed to significantly reduce the amount of pessimism (and optimism!) in the cell-timing design-analysis flow. Without such advances, a growing proportion of the clock period would be lost to margin. More recently there has been innovation at Synopsys to additionally target other forms of variation – those in the wires and vias – that have again been traditionally modeled as a flat margin. By addressing such variation in a programmatic way, we are again able to free up additional scope for more optimal power, performance and area for any given design.
The second class of margins has till now had less of a focus applied to it. These are the margins that are design-flow related. Systemic margins that exist due to the way that design flows have traditionally been constructed – the point tool solution. As designs are handed off from one level of accuracy and abstraction to the next, margins are used to smooth that transition or to account for differences in the way that aspects of the design are modeled. These systemic margins not only limit the maximum achievable power, performance, and area in a similar way to process margins, but can also negatively impact design convergence and ultimately time-to-results.
Doing it the right way
Synopsys Fusion Technology™ has been described as offering a solution to address these issues. But what really are these transformative benefits and how do they relate to the design flow at large?
If we go back to my 2000’s-esqe mix-tape design flow, the world of design seemed a lot easier then. This was because the interaction between tools in the flow was less important. Granted, you still wanted good correlation between synthesis and place-and-route for example, but you could always margin enough so that the handoff was made easier. With todays processes, margining in such a brute force way is both not productive or cost effective.
If I think about it, we likely left a significant amount of QoR on the table as everything was pre-conditioned to be “safe” in the hand-off. Safe is of course good, but safe is margin and margins are $$$.
If we now look at Fusion Technology within the Synopsys Design Platform, it aims to collapse the need for those margins by not just sharing technologies, but by making advanced quality-of-results (QoR) focused technologies available at any point in the flow. With Design Fusion we can now imagine a handoff flow where the place-and-route engineer is enabled to re-target for more optimal area, timing or power as the requirements change by leveraging logical re-synthesis much later in the flow. In a similar vein, the synthesis engineer can now evolve their flow by having access to advanced clock-tree-synthesis (CTS) engines when we are still in early phases of the design flow. For high-speed cores or places where multi-source CTS will later be deployed, this early insight into latencies and insertion delay can ensure that both under and overdesign do not occur. Reducing margins, and simplifying the flow for the end user.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.