Posted by Shekhar Kapoor on March 12, 2018
How machine learning can help meet PPA challenges and improve ECO optimization productivity.
It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer to home, in our own world of EDA and IC design, there is similar excitement about the potential of ML. The expectations run high, but key questions are: what are the meaningful opportunities for ML and the practical approaches for adoption to increase designer productivity?
There are several obvious areas in EDA that can benefit from ML, including modeling, parasitic extraction, routing and yield analysis. However, one area of increasing challenge for all designers is meeting the all-important power, performance, and area (PPA) targets – an ideal candidate for application of ML-based optimization. As designs continue to increase in complexity due to more features, advanced processes, variation, and more operating scenarios, it is causing the engineering change order (ECO) flows for design closure to become more data intensive and time consuming. This is becoming especially challenging as process technologies advance to 5nm and below.
Timing has always been a primary care-about in ECO cycles, but power has become an equally important criterion to achieve successful signoff at advanced nodes. However, timing and power optimization are contradictory challenges, e.g., reducing delays by sizing up cells increases dynamic and leakage power and vice versa. When performing power optimization, designers often dial up the accuracy using pessimism reduction technologies, such as path-based analysis (PBA) and parametric on-chip variation (POCV), and validate across “all operating modes” for “all process, voltage, and temperature (PVT) corners” to achieve best PPA results – but at the cost of significant runtime. The runtime problem is exacerbated at newer nodes, such as 5nm, with more optimization variables including more stringent spacing rules, more library cell options to cover the broad performance/power spectrum and hundreds of operating scenarios for full chip signoff.
Machine learning comes across as doctor-ordered formula for this symphony of complexities surrounding ECO power optimization. The most common ML method comprises the following steps: build a data bank, train the algorithm, create a model, and predict outcome for new input data. In the case of power optimization, it means learning from the ECO observed data and making fast and accurate predictions on power recovery choices without costly computations, for example, picking the best replacement cell for downsizing from, say 200 candidate library cells with different timing, power, and other complex characteristics.
Though collecting large amounts of data across design types and process nodes sounds attractive to improve model outcome, it is not an easy task and may not be required to achieve the desired quality of results (QoR). Most design decisions are relevant only in the context of their spatial or temporal proximity with-respect-to design architecture and versions; so, training data based on uncorrelated design points may not improve QoR. An alternate and practical ML method is “Active Learning,” which interacts with the optimization engine on-the-fly to build relevant learning models based on local design data. This significantly simplifies the optimization path to achieve signoff PPA with faster turnaround time and less resource overhead, providing a strong incentive for adoption.
Synposys PrimeTime suite is widely recognized as a standard for timing and power ECO and signoff. Its broad usage experience across an extensive range of application designs and process nodes enables it to more effectively address growing PPA challenges in design closure while offering advanced productivity and resource-efficiency technologies including machine learning.
Machine learning excitement is indeed justified. It clearly has potential to bring significant value to EDA and design, especially for time-consuming ECO optimization steps to improve productivity and achieve targeted PPA. An active ML approach provides an effective practical method to enable designers to incorporate the technology easily into their design flows and regain their power in a smarter way.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.