Posted by Ruben Molina on March 12, 2018
For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction was a crucial element of STA and more importantly, to the timing models that are required to perform the analysis. Having moved on from STA and into the world of Rs and Cs, I realized that parasitic extraction is without a doubt, one of the most interesting and under-appreciated topics in EDA.
Whereas in the context of an STA flow, parasitic extraction is primarily limited to the extraction of interconnect parasitics, it becomes far more interesting when extraction delves into the underlying structures of the transistors and their connections to the metal layers. This will become especially true as process technologies move to 5nm and below.
It is well documented that FinFET technologies starting at 16nm/14nm have dramatically increased the amount of parasitic values that must be extracted vs. planar transistors. The fins of these 3D like architectures sprout numerous capacitive values that must be extracted to accurately model electrical behavior and ultimately, the timing characteristics of the devices. Because today’s 2.5D parasitic extraction engines are pattern based, there are many more patterns that should be learned for FinFET vs. planar transistor technologies. The need to develop a robust set of patterns for accuracy standards while meeting decreasing process rollout cycles puts significant pressure on EDA and foundry vendors.
However, there is yet another challenge for new technologies being considered at 5nm and below. At these ever smaller geometries, foundries are challenged with reducing the channel lengths or widths of the fins to pack more gates in the same area while trying to maintain the same current densities. Trying to control these short channel lengths with tri-gate implementations has led to either taller and thinner fins or even more exotic structures like gate-all-around, which involves wrapping the gate around a cylindrical structure called a nano-wire. Other variants involve deforming these wires to more oblong type shapes referred to as nano-slabs or nano-sheets. The problem with a nano based structure and, to a lesser extent, taller and thinner FinFETs is these structures are becoming inherently more non-rectilinear in their physical profiles.
The fact that many of these proposed shapes are curvilinear begs the question: is it time for more mainstream use of 3D extraction tools known as field solvers? The field solver, as you might recall, has the advantage of not requiring a pattern matching methodology to estimate parasitics. Rather, the field solver can take any arbitrary shape and compute R and C values by solving complex EM equations. Of course, runtime costs can be mitigated with distributed processing and tile based solutions.
The additional good news in moving to 3D field solvers is that foundry certifications become a bit simpler since the golden values for the world’s leading foundries are based on the 3D field solvers themselves.
Synopsys extraction technologies have long been the standard reference of golden parasitics, from TCAD tool flows using Raphael XT to library characterization and critical net extraction using QuickCap and finally gate level extraction of interconnect parasitics using StarRC. Together, these tools provide a complete solution from the inception of the process, to final chip delivery.
Whichever way process technologies head, it’s becoming clear that 3D field solvers will play a dominant role in both the development of process technologies and the transistor/gate level architectures that are derived from them. As foundries move towards nano-wire and gate-all-around architectures, the extraction of parasitics at 5nm and below will bring a whole new level of appreciation from those involved in the development of these technologies, especially one former STA marketeer.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.