An often-overlooked cause of hold violations no longer can be ignored Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that. Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout. However, even after extensive signoff analysis, silicon failures still occur. The most critical and common silicon failures, the ones that need silicon re-spins to fix, are designs with hold violations. Some paths in silicon are just faster than signoff predicted, resulting in the chip being dead on arrival.
Why the cloud is becoming necessary in complex designs. Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool suppliers to look more seriously into cloud-based solutions?
What moving to the latest transistor types will mean for IC designers.
As test pattern compression falls behind, new techniques are needed to keep test times in check. Since the early days when semiconductor devices contained a mere handful of gates, the manufacturing test world has been focused on how to detect the greatest number of potential defects in the shortest amount of time. This fundamental goal has not changed over the years and continues at 5nm and beyond.
Complex process and layout rules for finFET processes have a big impact on the decisions made during synthesis. For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion.
For more precise static timing analysis with less uncertainty, rethink the idea of timing models.
As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which brings me to the topic of power integrity and how to best build robustness into silicon – a very beautiful thing.
How machine learning can help meet PPA challenges and improve ECO optimization productivity.
For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction was a crucial element of STA and more importantly, to the timing models that are required to perform the analysis. Having moved on from STA and into the world of Rs and Cs, I realized that parasitic extraction is without a doubt, one of the most interesting and under-appreciated topics in EDA.
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.