For more precise static timing analysis with less uncertainty, rethink the idea of timing models. When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as […]
These Aren’t Your Fathers’ Design Flows It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40-nanometers was the most advanced node that I ever designed SoC’s at and, although it wasn’t easy back then, it pales against the myriad of […]
As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how […]
How machine learning can help meet PPA challenges and improve ECO optimization productivity. It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept […]
For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction […]
Thinking 2 steps ahead to address future challenges at 5nm and below.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.