An often-overlooked cause of hold violations no longer can be ignored Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that. Once the performance goals are met then the attention […]
Why the cloud is becoming necessary in complex designs. Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not […]
What moving to the latest transistor types will mean for IC designers. When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did […]
As test pattern compression falls behind, new techniques are needed to keep test times in check. Since the early days when semiconductor devices contained a mere handful of gates, the manufacturing test world has been focused on how to detect the greatest number of potential defects in the shortest amount of time. This fundamental goal […]
Complex process and layout rules for finFET processes have a big impact on the decisions made during synthesis. For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area […]
For more precise static timing analysis with less uncertainty, rethink the idea of timing models. When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as […]
These Aren’t Your Fathers’ Design Flows It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40-nanometers was the most advanced node that I ever designed SoC’s at and, although it wasn’t easy back then, it pales against the myriad of […]
As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how […]
How machine learning can help meet PPA challenges and improve ECO optimization productivity. It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept […]
For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction […]
Thinking 2 steps ahead to address future challenges at 5nm and below.
Jim is the Director of Product Marketing for NanoTime.
Bernie is Director of Product Marketing for Synthesis.
Dr. Steve Pateras
Steve is Senior Director of Marketing for Test Automation.
Kenneth serves as Sr. Staff Product Marketing Manager with focus on In-design Rail Analysis.
Shekhar serves as the Director of Product Marketing for PrimeTime Static Timing Analysis.
Ruben serves as the Director of Product Marketing for StarRC Extraction and In-design Rail Analysis.
Mark serves as Technical Marketing Manager with a focus on IC Compiler II place-and-route.