InFormal Chat


Leave no stone unturned with AIP+VIP

You are verifying a complex AI or networking chip and found a test failing due to transaction or packet mismatch by scoreboards. As a verification engineer, you would celebrate that you broke the core design intent and found a bug! After hours/days of debugging, all that’s found is a signal on AHB/AXI interface was not connected or a protocol was not followed correctly. Not really a highly effective use of everyone’s time, is it?

SoCs today are equipped with many standard on-chip and off-chip communication protocols to interact with processor cores, memory subsystems, and peripherals. These protocols range from simple APB interface to read or write control/status registers, all the way to complex coherent interfaces, ensuring data integrity. Given the overwhelming nature of verification, it’s more efficient for designers to verify the core functionality of these interfaces using off-the-shelf Verification IP (VIP) and Assertion IPs (AIP).

Synopsys VIPs and AIPs are pre-verified and are proven with many customers’ designs to ensure compliance with standard protocols. A common question is, what’s the difference between VIP and AIPs? They not only differ in the way they are implemented, but offer specific advantages and complement each other for exhaustive verification. Synopsys VIP provides a built-in verification plan, sequences, protocol checks and functional coverage for accelerated verification closure. These are based on next-generation architecture and implemented in native SystemVerilog/UVM, which eliminates the need for language translation wrappers that affect performance and ease-of-use. While VIPs are mainly coded with behavioral, non-synthesizable constructs, Assertion IPs on the other hand are implemented using SystemVerilog synthesizable assertions and cover properties. AIPs are reusable across simulation, formal, and emulation and optimized for runtime and memory performance.

VIP consists of standard components like driver, monitor and scoreboard and are natively integrated with Verdi protocol and performance analyzer for faster debug and performance verification. In addition, source code Test Suites are also available to jump start verification. AIPs, on the other hand, do not have any drivers to drive transactions to the DUT interface and are not directly useful to verify standalone IPs in simulation, where VIPs are better fit. But with their concise and plug-and-play kind of implementation, are efficient to use in SubSystem or SoCs simulations to monitor and check the interface behavior. They have the ability to pin-point root cause of the failures closer to the signals and time of failures, allowing efficient debugging at the higher level w/ Verdi Waveform Debugger.

Unique advantages of AIPs come from their implementation using SVA and bind constructs. AIP instantiation is done through SystemVerilog bind construct which could bind it to a design module/interface or a specific instance. This enables efficient instantiation of AIPs for subsystem/SoC. E.g. an AHB AIP when bound to a AHB SystemVerilog interface, it will be automatically bound to all the design instances in the SoC where AHB interface is used. Also configuration of these AIPs is done through parameterization which further simplifies the setup. Assertions and coverage properties could be globally turned ON/OFF or selectively under exception scenarios.

Synopsys VC Formal customers use these AIPs with Formal Register Verification (FRV) and Formal Property Verification (FPV) apps for exhaustive verification to find corner case bugs. FRV uses these AIPs to model the register interface and ensure correct reading/writing of configuration registers per register specification. FPV enables exhaustive verification of the interface protocols with a rich set of properties available in AIP; assertions ensure that protocol is followed under any legal combination of input scenarios while coverage helps measure its effectiveness. Once IPs are thoroughly verified in formal, these AIPs are promoted to subsystem or SoCs in simulation or emulation for further checks and efficient debug. Coverage collected using cover properties in AIPs can be integrated to other simulation coverage metrics as well as integrated to verification planner to close the loop.

In summary, Synopsys AIPs and VIPs are helping design and verification teams across enterprises to focus on the core intent of their chip while alleviating the concerns of interface protocols. While VIPs with driver can be used across IP, subsystem and SoC level verification in simulation; AIPs are used in formal property verification at IP level and then subsequently at subsystem/SoC verification using simulation and emulation. This complementary use of VIPs and AIPs enables finding all types of bugs and ensure high quality verification signoff.

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