Posted by Ravindra Aneja on April 12, 2018
It should not be news to the readers that Formal verification is an integral part of verification flows for the majority of leading edge SoC design and IP companies. A good indicator for this is the amount of papers, posters and tutorials presented at recent industry events/conferences in Silicon Valley.
Formal verification was very well represented at DVCon 2018 in San Jose and SNUG Silicon Valley at Santa Clara convention center. At DVCon 2018, there were 7 papers, 5 posters and 6 tutorials covering various aspects and applications of Formal verification.
At DVCon 2018, Synopsys had a tutorial “Formal Verification – Breaking Through the Knowledge Barrier” where industry experts shared information on methodology and techniques that they have been using to solve hard verification problems. This tutorial was presented by Shaun Feng from Samsung, Syed Suhaib from Nvidia, Mandar Munishwar from Qualcomm and Iain Singleton from Synopsys.
Synopsys also held a panel “Conquering Formal Verification: Go Deep or Go Broad?” where industry experts (From left to right in the picture: Erik Seligman from Intel, Shaun Feng from Samsung, Ashish Darbari from Axiomise Ltd. and Mandar Munishwar from Qualcomm) discussed if users need to deploy Formal Apps broadly or invest in deep Formal property checking. The answer was both and it really depends on users’ needs. There was also discussion about solving hard verification problems by going deep as the only way to get management’s attention, followed by broadening use of Formal Apps in future designs. It was a very lively discussion and the best panel discussion I have seen at a panel in last few years.
Poster “Fast Track Formal Verification Signoff” submitted jointly by Mandar Munishwar from Qualcomm and Xiaolin Chen, Arunava Saha and Sandeep Jana from Synopsys won the second best poster award. In this paper, authors discussed how fault injection techniques combined with Formal can be leveraged to achieve Formal Signoff.
Moving forward to SNUG Silicon Valley last month, we had a full day track dedicated to Formal verification. We had papers from Cavium and SK Hynix and two tutorials from Synopsys. Saurabh Shrivastava from Cavium presented on how his team leveraged Formal verification to verify software configurable blocks for SDN designs. Yuri Tatarnikov from SK Hynix presented on how he has been using Formal verification to develop and verify assertion IPs for standard protocols. We hosted a Synopsys tutorial on shift left in verification for USB IP using VC Formal. In this tutorial, Garett Choy from the Synopsys USB IP team shared a case study on how Formal verification was used to reduce cost per bug (time and effort it takes to catch a bug and ensure bug fix is comprehensive), which achieved significantly better quality of verification. The second Synopsys tutorial was presented by Anders Nordstrom and yours truly, in this tutorial we discussed new Formal Apps (Security, X-prop and Registers verification) available in VC Formal.
At SNUG after party, a new book titled “Finding Your Way Through Formal Verification” was launched, it is co-authored by Bernard Murphy from SemiWiki, Manish Pandey and Sean Safarpour from Synopsys. You can download a copy at https://www.synopsys.com/verification/static-and-formal-verification/formal-book.html
For any DVCon conference pass holders who didn’t get a chance to attend, DVCon proceedings are available at http://proceedings.dvcon.org/proceedings/Login.aspx
If you did not get a chance to attend SNUG, SNUG proceedings are available at https://www.synopsys.com/community/snug/snug-silicon-valley/location-proceedings-2018.html
This large amount of participation from Formal verification users at these conferences proves (pun intended) that Formal verification adoption is expanding and is main stream now.