Posted by Anders Nordstrom on June 14, 2017
As I prepare to go to Austin, pouring through the extensive schedule trying to figure out which sessions to attend, I realize there is more Formal than ever at DAC. I feel like a kid in a candy store, so much candy – so little time. How can I choose the tastiest Formal presentations? As usual, there are theoretic academic presentations about algorithms but also an entire session of Formal goodies: “New Frontiers in Formal Verification”.
The papers and presentations on algorithms are important to enable next generation tool features and performance improvements. But, if you are not sure about the difference between BDD and SAT, you probably won’t feel entirely at home there.
What I find most exciting at this upcoming DAC, and where I will be heading, is to hear Formal users tell what kind of problems they are solving and how they are using the commercially available Formal tools.
The sweetest session is of course “New Frontiers in Formal Verification”. It looks like an interesting set of papers from among others TI, Samsung, Renesas and AMD covering areas as diverse as Formal verification of mixed signal designs, architectural Formal and usage of IP-XACT.
The paper on Formal techniques for effective co-verification of HW and SW sound interesting and goes in my candy bag. I wonder if it is a nearby advance or a far frontier in the so aptly named session on Tuesday afternoon.
On the exhibition floor, there are lots of Formal Verification presentations at various vendor booths. The best selection of Formal candy can be found in the Oski Technology booth, where Synopsys is presenting “Accelerating Verification Flows with Formal Technologies” on Monday at 1 pm. With 4 presentations per day, you are sure to find a flavor of Formal you like.
For other presentations on Formal, it looks like presenters are playing musical chairs. Everybody is presenting somewhere else… You’ll find Samsung, Oski, ARM, Qualcomm and others scattered across the floor.
Last but not the least, don’t miss the daily poster sessions for a collection of Formal treats. My favorite of course is “Formal Connectivity Checking Metrics” presented on Wednesday afternoon at 5 pm on the exhibit floor.
If all these Formal presentations got you interested in learning more, there is always “Thursday is Training Day” with a tutorial on Formal Verification using SystemVerilog Assertions as a sweet finish on DAC.
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